Showing papers on "Low-power electronics published in 1999"

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Abstract: Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

Abstract: Modern microprocessors employ one or two levels of on-chip caches to bridge the burgeoning speed disparities between the processor and the RAM. These SRAM caches are a major source of power dissipation. We investigate architectural techniques, that do not compromise the processor cycle time, for reducing the power dissipation within the on-chip cache hierarchy in superscalar microprocessors. We use a detailed register-level simulator of a superscalar microprocessor that simulates the execution of the SPEC benchmarks and SPICE measurements for the actual layout of a 0.5 micron, 4-metal layer cache, optimized for a 300 MHz, clock. We show that a combination of subbanking, multiple line buffers and bit-line segmentation can reduce the on-chip cache power dissipation by as much as 75% in a technology-independent manner.

A coding framework for low-power address and data busses

Abstract: This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f/sub 1/. Next, a variant of entropy coding function f/sub 2/ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f/sub 1/ and f/sub 2/ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 /spl mu/m CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes.

Models and algorithms for bounds on leakage in CMOS circuits

Abstract: Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

A novel low power energy recovery full adder cell

Abstract: A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low powerful adders; the transmission function adder (TFA) the dual value logic (DVL) adder and the fourteen transistor (14 T) full adder. The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder. The combination of low power and low transistor count makes the new SERF cell a viable option for low power design.

Ultra-low power digital subthreshold logic circuits

Abstract: Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.

Low-power bandgap references featuring DTMOSTs

Abstract: This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 /spl mu/W; the die area is 0.063 mm/sup 2/ in a standard digital 0.35-/spl mu/m CMOS process. The second bandgap reference circuit aims at high accuracy operation (/spl sigma/=0.3%) without trimming. It consumes approximately 5 /spl mu/W from a 1.8-V supply voltage and occupies 0.06 mm/sup 2/ in a standard 0.35-/spl mu/m CMOS process.

Design of high-Q varactors for low-power wireless applications using a standard CMOS process

Abstract: New applications such as wireless integrated network sensors (WINS) require radio-frequency transceivers consuming very little power compared to usual mainstream applications, while still working in the ultra-high-frequency range. For this kind of application, the LC-tank-based local oscillator remains a significant contributor to the overall receiver power consumption. This statement motivates the development of good on-chip varactors available in a standard process. This paper describes and compares the available solutions to realize high-Q, highly tunable varactors in a standard digital CMOS submicrometer process. On this basis, quality factors in excess of 100 at 1 GHz, for a tuning ratio reaching two, have been measured using a 0.5-/spl mu/m process.

A low power hardware/software partitioning approach for core-based embedded systems

Abstract: We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping clusters of operations/instructions to a core that yields a high utilization rate of the involved resources (ALUs, multipliers, shifters...) and thus minimizing power consumption. Our approach is comprehensive since it takes into consideration the power consumption of a whole embedded system comprising a microprocessor core, application specific (ASIC) core(s), cache cores and a memory core. We report high reductions of power consumption between 35% and 94% at the cost of a relatively small additional hardware overhead of less than 16 k cells while maintaining or even slightly increasing the performance compared to the initial design.

A low-noise, low-power VCO with automatic amplitude control for wireless applications

Abstract: Voltage controlled oscillators (VCOs) used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase-noise levels while consuming minimal power. This paper presents the design challenges of a VCO with automatic amplitude control, which operates in the 300 MHz to 1.2 GHz frequency range using different external resonators. The VCO phase noise level is -106 dBc/Hz at 100-KHz offset from an 800-MHz carrier, and it consumes 1.6 mA from a 2.7-V power supply. An extensive phase-noise analysis is employed for this VCO design in order to identify the most important noise sources in the circuit and to find the optimum tradeoff between noise performance and power consumption.

Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Abstract: We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of "dominant leakage states" and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE. This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual V/sub t/ processes. In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low V/sub t/ transistors, but with 1/3 to 1/6 the stand-by current.

Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs

Abstract: In sub 1 V CMOS designs, especially around 0.5 V CMOS designs, the on-state drain current of MOSFET's shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Together with the low threshold voltage less than 0.2 V in the low-voltage CMOS, a possibility of temperature instability increases. The paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFET's and 32-bit adder circuit in quarter micron CMOS technology with low threshold voltage of 0.25 V.

A physical alpha-power law MOSFET model

Abstract: A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original alpha-power law model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: 1) a subthreshold region of operation for evaluating the on/off current tradeoff that becomes a dominant low power design issue as technology scales, 2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to the National Technology Roadmap for Semiconductors (NTRS) extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration.

Low power synthesis of dual threshold voltage CMOS VLSI circuits

Abstract: The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits With the supply voltage at 1 V and threshold voltage as low as 02 V the subthreshold leakage power of transistors starts dominating the dynamic power Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption We present a near-optimal approach to synthesize low static power CMOS VLSI circuits with two threshold voltages that reduces power consumption compared with a previous approach by up to 2945% Also, presented is a technique which finds static power optimal configurations for CMOS VLSI circuits when an arbitrary number of threshold voltages are allowed

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

Abstract: We demonstrate that, there is an optimum reverse body bias, unique to any technology generation, that minimizes the standby leakage power consumption of an IC design implemented in that technology. We also show: (1) the optimum reverse body bias value reduces by /spl sim/2X per technology generation, and (2) the maximum achievable leakage power reduction by reverse body biasing diminishes by /spl sim/4X per generation under constant field technology scaling scenario. Optimum point occurs as a result of reduction in subthreshold leakage and an increase injunction band-to-band tunneling leakage with applied reverse bias. Therefore, new junction engineering techniques to reduce the bulk band-to-band tunneling leakage current component across the junction are needed to preserve the effectiveness of reverse body biasing for standby leakage control in future technologies.

Ultra low-voltage/low-power digital floating-gate circuits

Abstract: This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits The effective threshold voltage seen from a control gate is adjusted during a UV-light-activated tuning procedure The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV light through an activated conductance between the power rails and the floating gates Measured results are provided for gates operating down to 04-V power supply, using a standard double-poly CMOS process

Register transfer level power optimization with emphasis on glitch analysis and reduction

Abstract: We present design-for-low-power techniques for register-transfer level (RTL) controller/data path circuits. We analyze the generation and propagation of glitches in both the control and data path parts of the circuit. In data-flow intensive designs, glitching power is primarily due to the chaining of arithmetic functional units. In control-flow intensive designs, on the other hand, multiplexer networks and registers dominate the total circuit power consumption, and the control logic can generate a significant amount of glitches at its outputs, which in turn propagate through the data path to account for a large portion of the glitching power in the entire circuit. Our analysis also highlights the relationship between the propagation of glitches from control signals and the bit-level correlation between data signals. Based on the analysis, we develop techniques that attempt to reduce glitching power consumption by minimizing propagation of glitches in the RTL circuit. Our techniques include restructuring multiplexer networks (to enhance data correlations and eliminate glitchy control signals), clocking control signals, and inserting selective rising/falling delays, in order to kill the propagation of glitches from control as well as data signals. In addition, we present a procedure to automatically perform the well-known power-reduction technique of clock gating through an efficient structural analysis of the RTL circuit, while avoiding the introduction of glitches on the clock signals. Application of the proposed power optimization techniques to several RTL circuits shows significant power savings, with negligible area and delay overheads.

Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter

Abstract: A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies.

A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity

Abstract: A chip has been designed and tested to demonstrate the feasibility of an ultra-low-power, two-dimensional inverse discrete cosine transform (IDCT) computation unit in a standard 3.3-V process. A data-driven computation algorithm that exploits the relative occurrence of zero-valued DCT coefficients coupled with clock gating has been used to minimize switched capacitance. In addition, circuit and architectural techniques such as deep pipelining have been used to lower the voltage and reduce the energy dissipation per sample. A Verilog-based power tool has been developed and used for architectural exploration and power estimation. The chip has a measured power dissipation of 4.65 mW at 1.3 V and 14 MHz, which meets the sample rate requirements for MPEG-2 MP@ML. The power dissipation improves significantly at lower bit rates (coarser quantization), which makes this implementation ideal for emerging quality-on-demand protocols that trade off energy efficiency and video quality.

Mixed-V/sub th/ (MVT) CMOS circuit design methodology for low power applications

Abstract: Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

A high speed, 500 frames/s, 1024/spl times/1024 CMOS active pixel sensor

Abstract: The paper presents a high-speed (500 f/s) large-format 1 K/spl times/1 K 8 bit 3.3 V CMOS active pixel sensor (APS) with 1024 ADCs integrated on chip. The sensor achieves an extremely high output data rate of over 500 Mbytes per second and a low power dissipation of 350 mW at the 66 MHz master clock rate. Principal architecture and circuit solutions allowing such a high throughput are discussed along with preliminary results of the chip characterization.

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Abstract: We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Analog circuit performance and process scaling

Abstract: With newer CMOS processes, minimum transistor dimensions decrease and the supply voltage steadily gets lower. This trend is driven by the performance of digital systems: their level of performance (speed) increases while at the same time the cost (power consumption and die area) decreases. However, the performance of analog or mixed-signal circuits in newer CMOS generations does not necessarily improve. In this paper, trends in CMOS technology and supply voltage in relation to the performance of analog blocks in mixed-signal chips are analyzed. First, a relation for the absolute minimum power consumption of analog circuits is derived, based on a specific signal-to-noise and-distortion ratio (SINAD) over the full signal bandwidth. This limit shows that power consumption increases considerably with decreasing supply voltage, even at a constant performance level. The second part of this paper illustrates the trend in power consumption for actual analog circuits with SINAD demands. A quasi-differential CMOS voltage-follower circuit is used as a demonstration vehicle. In newer CMOS processes, the MOS transistors in the circuit get better, which tends to decrease the power consumption. The combined effect of the improving MOS transistors and the decreasing supply voltage is that power consumption at constant performance decreases down to about the 0.25-0.35-/spl mu/m CMOS generations, and increases with newer CMOS generations thereafter. Ultimately, low supply voltages limit circuit feasibility or performance feasibility of analog circuits in newer CMOS processes.

System-level power optimization: techniques and tools

Abstract: This tutorial presents a cohesive view of power-conscious system-level design We consider systems as consisting of a hardware platform executing software programs We address the problems of power estimation and minimization for such systems We consider the major constituents of systems: processors, memories and communication resources We analyze power dissipation in these components and we survey computer-aided power reduction techniques We also consider global system-level control schemes, such as dynamic power management We conclude by pointing out further research problems which are still open in this domain

A physical alpha-power law MOSFET model

Abstract: A new compact physics-based alpha-power law MOSFET model is introduced to enable projections of low power circuit performance for future generations of technology by linking the simple mathematical expressions of the original Alpha-Power Law Model with their physical origins. The new model, verified by HSPICE simulations and measured data, includes: (1) a subthreshold region of operation for evaluating the on/off current trade-off that becomes a dominant low power design issue as technology scales, (2) the effects of vertical and lateral high field mobility degradation and velocity saturation, and (3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate a 2X-performance opportunity compared to NTRS extrapolations for the 250, 180, and 150 nm generations subject to maximum leakage current estimates of the roadmap. NTRS and model calculations converge at the 70 nm technology generation, which exhibits pronounced on/off current interdependence for low power gigascale integration (GSI).

Technology and design challenges for low power and high performance [microprocessors]

Abstract: We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks and interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.

Voltage-clock scaling for low energy consumption in real-time embedded systems

Abstract: Low power and energy consumption will always be an essential requirement in many real-time embedded applications. Voltage scaling is a relatively novel approach to reducing energy consumption. The idea is that a processor can be run either at high or at low voltage: at high voltage, the clock rate is high but so is the power consumption; at low voltage the clock rate is lower, but the power consumption drops by a greater factor. This immediately suggests a powerful approach to lowering energy consumption in real-time systems. In this paper we introduce static and dynamic algorithms to control processor voltage to reduce energy consumption. We demonstrate by simulation that our algorithms can significantly reduce total energy consumption.

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems

Abstract: In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 /spl mu/m CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.

Reducing cross-coupling among interconnect wires in deep-submicron datapath design

Abstract: As CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bus structures very data-dependent. Reducing the cross-coupling capacitance is crucial for achieving high-speed as well as lower power operation. In this paper, we propose two interconnect layout design methodologies for minimizing the "cross-coupling effect" in the design of full-custom datapath. Firstly, we describe the control signal ordering scheme which was shown to minimize the switching power consumption by 10% and wire delay by 15% for a given set of benchmark examples. Secondly, a track assignment algorithm based on evolutionary programming was used to minimize the cross-coupling capacitance. Experimental results have shown that chip performance improvement of as much as 40% can be obtained using the proposed interconnect schemes in various stages of the datapath layout optimization.