Showing papers on "Memistor published in 2016"

A magnetic synapse: multilevel spin-torque memristor with perpendicular anisotropy.

Abstract: Memristors are non-volatile nano-resistors which resistance can be tuned by applied currents or voltages and set to a large number of levels. Thanks to these properties, memristors are ideal building blocks for a number of applications such as multilevel non-volatile memories and artificial nano-synapses, which are the focus of this work. A key point towards the development of large scale memristive neuromorphic hardware is to build these neural networks with a memristor technology compatible with the best candidates for the future mainstream non-volatile memories. Here we show the first experimental achievement of a multilevel memristor compatible with spin-torque magnetic random access memories. The resistive switching in our spin-torque memristor is linked to the displacement of a magnetic domain wall by spin-torques in a perpendicularly magnetized magnetic tunnel junction. We demonstrate that our magnetic synapse has a large number of intermediate resistance states, sufficient for neural computation. Moreover, we show that engineering the device geometry allows leveraging the most efficient spin torque to displace the magnetic domain wall at low current densities and thus to minimize the energy cost of our memristor. Our results pave the way for spin-torque based analog magnetic neural computation.

Emerging Memristor-Based Logic Circuit Design Approaches: A Review

Abstract: This article is a comprehensive review of the state-of-theart of memristor-based logic circuit design concepts of the recent literature. Amongst all the identified circuit design approaches, those discussed here are all based on collective memristive dynamics and share a number of common characteristics which facilitate their comparison. The focus is on the evolution of the memristor-based logic circuit design strategies from the early proposed sequential stateful logic up to most recently published design schemes which support parallel processing of the applied input signals. The main operational properties of all the selected computational concepts are presented in an accessible manner, aiming to serve as an informative cornerstone for students and scientists who wish to get involved in emerging memristive logic circuit research and development.

Memristor crossbar deep network implementation based on a Convolutional neural network

Abstract: This paper presents a simulated memristor crossbar implementation of a deep Convolutional Neural Network (CNN). In the past few years deep neural networks implemented on GPU clusters have become the state of the art in image classification. They provide excellent classification ability at the cost of a more complex data manipulation process. However once these systems are trained, we show that the analog crossbar circuits in this paper can highly parallelize the recognition phase of a CNN algorithm. One of the drawbacks of using memristors to carry out computations is that the data stored will likely have less precision when compared to typical 32-bit floating point memory. However, we show the proposed system is capable of operating with zero loss in classification accuracy if the memristors utilized are able to store at least 16 unique values (essentially acting as 4-bit devices). To the best of our knowledge, this is the first paper that presents a memristor based circuit for implementing CNN recognition. This is also the first paper that provides a circuit for precise memristor based analog convolution.

MNSIM: Simulation platform for memristor-based neuromorphic computing system

Abstract: Memristor-based neuromorphic computing system provides a promising solution to significantly boost the power efficiency of computing system. Memristor-based neuromorphic computing system has a wide range of design choices, such as the various memristor crossbar cell designs and different parallelism degrees of peripheral circuits. However, a memristor-based neuromorphic computing system simulator, which is able to model the system and realize an early-stage design space exploration, is still missing. In this paper, we develop a memristor-based neuromorphic system simulation platform (MNSIM). MNSIM proposes a general hierarchical structure for memristor-based neuromophic computing system, and provides flexible interface for users to customize the design. MNSIM also provides a detailed reference design for large-scale applications. MNSIM embeds estimation models of area, power, and latency to simulate the performance of system. To estimate the computing accuracy, MNSIM proposes a behavior-level model between computing error rate and crossbar design parameters considering the influence of interconnect lines and non-ideal device factors. The error rate between our accuracy model and SPICE simulation result is less than 1%. Experimental results show that MNSIM achieves more than 7000 times speed-up compared with SPICE and obtains reasonable accuracy. MNSIM can further estimate the trade-off between computing accuracy, energy, latency, and area among different designs for optimization.

Stochasticity Modeling in Memristors

Abstract: Diverse models have been proposed over the past years to explain the exhibiting behavior of memristors, the fourth fundamental circuit element. The models varied in complexity ranging from a description of physical mechanisms to a more generalized mathematical modeling. Nonetheless, stochasticity, a widespread observed phenomenon, has been immensely overlooked from the modeling perspective. This inherent variability within the operation of the memristor is a vital feature for the integration of this nonlinear device into the stochastic electronics realm of study. In this paper, experimentally observed innate stochasticity is modeled in a circuit compatible format. The model proposed is generic and could be incorporated into variants of threshold-based memristor models in which apparent variations in the output hysteresis convey the switching threshold shift. Further application as a noise injection alternative paves the way for novel approaches in the fields of neuromorphic engineering circuits design. On the other hand, extra caution needs to be paid to variability intolerant digital designs based on nondeterministic memristor logic.

Generalized boundary condition memristor model

Abstract: SUMMARY A number of resistive switching memories exhibit activation-based dynamical behavior, which makes them suitable for neuromorphic and programmable analog filtering applications. Because the Boundary Condition Memristor (BCM) model accounts for tunable activation thresholds only at the on and off boundary states, it is not quantitatively accurate in the description of these kinds of memristors and in the investigation of their circuit applications. This paper introduces the Generalized Boundary Condition Memristor (GBCM) model, preserving the features of the BCM model while allowing, further, an ad-hoc tuning of activation-based dynamics, which enables an appropriate modulation of the conditions under which memristors may operate as storage elements or data processors. A simple circuit implementation of the novel model is presented, and time-efficient simulations confirming the improvement in modeling accuracy over the BCM model are shown. As a proof-of-concept for the suitability of the GBCM model in the exploration of the full potential of memristors in neuromorphic circuits and programmable analog filters, this paper adopts it to model fundamental synaptic rules governing the mechanisms of learning in neural systems and to gain some insight into key issues in the design of a couple of filters. Copyright © 2015 John Wiley & Sons, Ltd.

History Erase Effect in a Non-Volatile Memristor

Abstract: This work presents a detailed study of the nonlinear dynamics of a tantalum oxide memristor recently fabricated at Hewlett Packard Labs. Our investigations uncover direct current, quasi-static, and alternating current behavior of the nanodevice. A thorough study of the dynamics emerging in the nanoscale element under various input/initial condition combinations reveals a fundamental property of the tantalum oxide device, which was unnoticed so far. The initial condition has no effect on the steady-state operation of the memristor under non-zero input. This property, known as fading memory in system theory, implies the uniqueness of asymptotic behavior of the memristor. The progressive input-induced memory erase phenomenon is solely determined by the switching dynamics of the nanodevice, mathematically described by the state evolution function, which governs the rate of evolution of the memristor state. A constant-sign DC input will activate on or off switching dynamics only. Consequently, due to the limited on/off memductance ratio, the memristor will asymptotically attain a fully-conducting or highly-resistive state, irrespective of the initial condition. Most interestingly, under AC periodic excitations, it is the pronounced asymmetry in the state dependence of on and off switching processes which is at the basis of the reported history erase effect. It is important to point out that this novel fading memory phenomenon does not compromise the nonvolatile behavior of the nanostructure. In fact, despite the device may be stimulated so as to forget its past history, it still has a continuum of analog nonvolatile memory states.

A new floating memristor emulator and its application in frequency-to-voltage conversion

Abstract: In this paper a new circuit for practical emulation of a floating memristor is presented. The circuit is simple, flexible and built around the current-feedback operational-amplifier and avoids the use of analog-to-digital and digital-to-analog converters and the analog multiplier. The circuit is simpler than the very few available similar circuits. The application of the proposed floating memristor emulator in designing an FM-to-AM converter confirms the functionality of the proposed circuit. Experimental results are included.

Information-Theoretic Sneak-Path Mitigation in Memristor Crossbar Arrays

Abstract: In a memristor crossbar array, functioning as a memory array, a memristor is positioned on each row–column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this paper, we study the sneak path problem in crossbar arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are modeling the error channel induced by sneak paths, a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method, we match a constraint on the array content that guarantees sneak-path free readout, determine the resulting capacity, and provide an efficient encoder that achieves the capacity.

A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy

Abstract: Matrix-vector multiplication, as a key computing operation, has been largely adopted in applications and hence greatly affects the execution efficiency. A common technique to enhance the performance of matrix-vector multiplication is increasing execution parallelism, which results in higher design cost. In recent years, new devices and structures have been widely investigated as alternative solutions. Among them, memristor crossbar demonstrates a great potential for its intrinsic support of matrix-vector multiplication, high integration density, and built-in parallel execution. However, the computation accuracy and speed of such designs are limited and constrained by the features of crossbar array and peripheral circuitry. In this work, we propose a new memristor crossbar based computing engine design by leveraging a current sensing scheme. High operation parallelism and therefore fast computation can be achieved by simultaneously supplying analog voltages into a memristor crossbar and directly detecting weighted currents through current amplifiers. The performance and effectiveness of the proposed design were examined through the implementation of a neural network for pattern recognition based on MNIST database. Compared to a prior reported design, ours increases the recognition accuracy 8.1% (to 94.6%).

Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications

Abstract: Conventional charge-based memory usage in low-power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM), additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memristor and spin-transfer torque (STT)-RAM, as potential universal memory candidates to replace traditional ones. Both of these nonvolatile memories support zero leakage and low-voltage operation during read access, which makes them ideal for devices with long sleep time. To date, high write energy for both memristor and STT-RAM is one of the major inhibitors for adopting the technologies. The primary contribution of this paper is centered on addressing the high write energy issue by trading off retention time with noise margin. In doing so, the memristor and STT-RAM power has been compared with the traditional six-transistor-SRAM-based memory power and potential application in wireless sensor nodes is explored. This paper uses 45-nm foundry process technology data for SRAM and physics-based mathematical models derived from real devices for memristor and STT-RAM. The simulations are conducted using MATLAB and the results show a potential power savings of 87% and 77% when using memristor and STT-RAM, respectively, at 1% duty cycle.

A class of versatile circuits, made up of standard electrical components, are memristors

Abstract: Summary In this paper, we propose a whole class of memristor circuits. Each element from the class consists of the cascade connection between a static nonlinear two-port and a dynamic one-port. The class may be divided into two subclasses depending on the input variable (voltage or current). Within each of these subclasses, two further sets of memristor circuits may be distinguished according to which output voltage and current of the two-port represents one of the system states. The simplest memristor circuits make only use of purely passive elementary components from circuit theory, an absolute novelty in this field of research. Thus they are suitable circuit primers for the introduction of the topic of memristors to undergraduate students. A sample circuit is built using discrete devices and its memristive nature is validated experimentally. In case the one-port is purely passive, the proposed circuits feature volatile memristive behavior. Allowing active devices into the dynamic one-port, non-volatile dynamics may also emerge, as proved through concepts from the theory of nonlinear dynamics. Given the generality of the proposed class, the topology of the emulators may be adjusted so as to induce a large variety of dynamical behaviors, which may be exploited to accomplish new signal processing tasks, which conventional circuits are unable to perform. Copyright © 2015 John Wiley & Sons, Ltd.

Dot-product engine as computing memory to accelerate machine learning algorithms

Abstract: Currently, intense work is underway to develop memristor crossbar arrays for high density, nonvolatile memory applications. However, another capability of memristor crossbars - natural dot-product operation for vectors and matrices - holds even greater potential for next-generation computing, including accelerators, neuromorphic computing, and heterogeneous computing. In this paper, we present a dot-product engine (DPE) based on memristor crossbars optimized for dense matrix computation, which is dominated in most machine learning algorithms. We explored multiple methods to enhance DPE's dot-product computing accuracy. Moreover, instead of training crossbars, we try to directly use existing software-trained weight matrices on DPEs so no heroic effort is needed to innovate learning algorithms for new hardware. Our results show that computations utilizing DPEs can achieve 1000 ∼ 10000 times better speed-efficiency product comparing to a state-of-art ASIC [1]. And machine learning algorithm utilizing DPEs can easily achieve software-level accuracy on testing. Both experimental demonstrations and data-calibrated circuit simulations are presented to demonstrate the realistic implementation of a memristor crossbar DPE.

The Generalized Metastable Switch Memristor Model.

Abstract: Memristor device modeling is currently a heavily researched topic and is becoming ever more important as memristor devices make their way into CMOS circuit designs, necessitating accurate and efficient memristor circuit simulations. In this paper, the Generalized Metastable Switch (MSS) memristor model is presented. The Generalized MSS model consists of a voltage-dependent stochastic component and a voltage-dependent exponential diode current component and is designed to be easy to implement, computationally efficient, and amenable to modeling a wide range of different memristor devices.

A Digital Memristor Emulator for FPGA-Based Artificial Neural Networks

Abstract: FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain human brain-like functionalities at circuit-level. In this context, the memristor has been proposed as the electronic analogue of biological synapses, but the price of commercially available samples still remains high, hence motivating the development of HW emulators. In this work we present the first digital memristor emulator based upon a voltagecontrolled threshold-type bipolar memristor model. We validate its functionality in low-cost yet powerful FPGA families. We test its suitability for complex memrisive circuits and prove its synaptic properties in a small associative memory via a perceptron ANN.

Complete stability of feedback CNNs with dynamic memristors and second-order cells

Abstract: The paper considers a feedback cellular neural network CNN obtained by interconnecting elementary cells with an ideal capacitor and an ideal flux-controlled memristor. It is supposed that during the analogue computation of the CNN the memristors behave as dynamic elements, so that each dynamic memristor DM-CNN cell is described by a second-order differential system in the state variables given by the capacitor voltage and the memristor flux. The proposed networks are called DM-CNNs, that is CNNs using a dynamic D memristor M. After giving a foundation to the DM-CNN model, the paper establishes a fundamental result on complete stability, that is convergence of solutions toward equilibrium points, when the DM-CNN has symmetric interconnections. Because of the presence of dynamic memristors, a DM-CNN displays peculiar and basically different dynamic properties with respect to standard CNNs. First of all a DM-CNN computes during the time evolution of the memristor fluxes, instead of the capacitor voltages as for a standard CNN. Furthermore, when a steady state is reached, the memristors keep in memory the result of the computation, that is the limiting values of the fluxes, while all memristor currents and voltages, as well as all currents, voltages, and power in the DM-CNN vanish. Instead, for standard CNNs, currents, voltages, and power do not drop off when a steady state is reached. Copyright © 2016 John Wiley & Sons, Ltd.

Area efficient implementation of ripple carry adder using memristor crossbar arrays

Abstract: Memristor has drawn the attention of circuit designers for its non-volatility, and is considered as a viable candidate to replace CMOS technology in many applications. Another interesting characteristic of memristor is that it can be employed in crossbar array architecture that allows very high packing density. In addition to implementing high capacity storage systems, memristor can also be used to realize logic functions. In this paper, the Memristor Aided Logic (MAGIC) design style is used to map the NOR netlist of a given Boolean function to memristor crossbar arrays. Various optimization techniques have been used by scheduling the NOR gates to time steps in order to reduce the hardware cost. To illustrate the viability of the design methodology, full adder and ripple carry adder circuits have been studied and analyzed.

Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems

Abstract: As the fourth basic circuit element, memristor has a unique synapse-alike feature which demonstrates great potentials in neuromorphic circuit design. However, a large gap exists between the theoretical memristor characteristics and the actual device behavior. For example, though the continuous changing in resistance state is expected in neuromorphic circuit design, it is difficult to maintain arbitrary intermediate state. In addition, the stochastic switching behaviors have been widely observed in nano-scale memristor devices. In this work, we first developed a stochastic behavior model in order to facilitate the investigation on memristor-based hardware implementation. Our modeling was based on the statistical analysis of experimental data of ${\rm TiO }_{2}$ device. By leveraging the stochastic behavior of memristors, a random number generator was proposed. We also presented a macro cell design composed of multiple parallel connecting memristors which can be successfully used in implementing the weight storage unit and the stochastic neuron. The designs of these fundamental components provide a feasible solution in memristor-based hardware implementation of neural networks.

An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates

Abstract: Research on memristors have drawn wide attentionin recent years as these devices exhibit unique properties whichcan be used to perform various logic and memory operations. Memristor based memory systems are expected to replace flashmemory devices in the near future. In addition, synthesis andoptimization of boolean functions using memristors are becomingan important area of research. There are various logic designstyles for memristors that have been reported, among which theone that implements material implication operation forms thebasis of the present work. An IMPLY gate implements the impli-cation operation, and can be realized using only two memristorsand one resistance. In the present work, the widely availablesynthesis tool ABC is used for synthesizing an arbitrary booleanfunction into a netlist of IMPLY gates. To optimize the numberof memristors to be used for the realization, we propose anINVERSE-IMPLY gate for handling fanouts in the intermediatenetlist generated by the ABC tool. Synthesis experiments havebeen carried out on standard benchmark functions of up to 16variables, which show an overall improvement of 22.8% in thenumber of steps required for evaluation over an existing state-of-the-art method. For functions with 9 or more variables, theimprovement increases to 35.5%.

Ultra low-voltage ultra low-power memristor based band-pass filter design and its application to EEG signal processing

Abstract: Memristor has been claimed as the passive fourth fundamental circuit element in 1971. About four decades later, a physical realization which presents memristor behavior has resulted in significant interest on memristor and it is continuing to increase at a growing rate. Memristor can provide new possibilities in analog circuit design thanks to its properties which cannot be mimicked by older passive circuit elements. Since no practically available memristor exist on the market yet, obtaining of a practical implementation which behaves like a memristor is important from the point of view real-world circuit design. In this paper, an ultra low-voltage ultra low-power DTMOS-based memristor design is presented. Ultra low-voltage, ultra low-power operational amplifier and ultra low-voltage, ultra low-power multiplier are also designed to use in the implementation. Memristor design is composed of these two type active blocks using CMOS 0.18 µm process technology with symmetric ?0.25 V supply voltages. Our memristor is used in a second order Sallen---Key band-pass filter topology. Designed memristor-based Sallen---Key band-pass filter is then used for real electroencephalogram data processing. The simulation results show that the design of adjustable memristor memristance/memductance provides tunable filter parameters and without any significant distortion with appropriate parameter set even at ultra-low power levels and at very-low frequencies.

Process Variation Aware Design of Multi-Valued Spintronic Memristor-Based Memory Arrays

Abstract: The missing fourth passive element, predicted by L. Chua and denoted by memristor, has recently been in the research focus since its titanium dioxide thin film realization is reported by HP. Following that, the spintronic memristor, which is based on the magnetic tunneling junction, is presented as an alternative to the thin film memristor. The nano-scale geometry size of the memristor makes it hard to control its dimensions due to the process variation resulting from the fabrication process. This process variation results in yield degradation in the spintronic memristor-based memory arrays. This yield degradation is more significant when the spintronic memristor is utilized as a multi-valued memory elements. In this paper, the impact of the process variation on the spintronic memristor-based memory yield is discussed for the 1-bit, 2-bit, and ${n}$ -bit memory element. Moreover, two approaches are introduced to enhance the memory yield.

Modelling and characterization of dynamic behavior of coupled memristor circuits

Abstract: This paper explores the dynamic behavior of dual flux coupled memristor circuits in order to further ascertain fundamental theory of memristor circuits. Different cases of flux coupling are mathematically modelled where two memristors are connected in both series and parallel, with consideration given to the polarity of each device. The dynamic behavior is characterized based on the constitutive relations, with a variation of memductance represented in terms of flux, charge, voltage and current. The agreement between theoretical and simulation analyses affirm the memristor closure theorem with coupled memristor circuits behaving as a different type of memristor with higher complexity.

A neuromorphic ASIC design using one-selector-one-memristor crossbar

Abstract: The applications of memristors in neuromorphic computing have been extensively studied for its analogy to synapse. To overcome sneak path issue, nonlinear resistive selectors have been introduced to the design of memristor crossbar, enabling a high integration density and robust computing capability. However, the nonlinearity of such selectors also influences the computation accuracy of the vector-matrix multiplication performed on the memristor crossbar. In this work, we evaluate the impact of nonlinear resistive selectors on the computation robustness of a Hopfield spike-based pattern recognition system based on memristor crossbar technology. The methods that can suppress the adverse impact of the nonlinear selector on the system performance are also studied.

Simple generic memristor emulator for voltage-controlled models

Abstract: In recent times, memristors have drawn wide spread attention from the research community due to their potential applications in memory and various other systems. However, as of now, no solid state device could be designed to achieve the memristive behavior. The research community has been trying to build emulator circuits to study the behavior of the memristor due to the lack of the solid state memristor samples. In this paper, we introduce a generic and simple emulator circuit for a voltage controlled memristor. Although, the voltage-controlled memristor models are of great importance, no significant research has been done to build emulator circuits for this type of memristor. We propose an emulator circuit design comprised of only two second generation current conveyers (CCII+) and one multiplier to achieve the hysteretic behavior of the memristor. We also present the mathematical modeling and SPICE simulation of the proposed emulator circuit. Experimental results show proper matching with the results obtained from the SPICE simulation.

An a VLSI driving circuit for memristor-based STDP

Abstract: The main goal in realizing a VLSI (analog VLSI) systems able to mimic functionalities of biological neural networks is pointed to the reproduction of realistic synapses. Indeed, because of the relative high synapse/neuron ratio, especially in the case of extremely dense networks (i.e., reproduction of a real scenario), synapses represent a considerable limitation in terms of waste of silicon area and power consumption as well. Thanks to advancement made in the implementation of memristor, the interest in bio-inspired neural network design has been renewed. Memristors have tunable resistance which depends on its past state; this is analogous to the operating mode of biological synapses. In this paper, we present the circuit implementation of a simple memristor-based neural network. Here, we propose a driving circuit model that not requires specific shape input pulses to change the memristor conductance (i.e., synaptic strength), but it can be driven by arbitrary shaped input pulses. Moreover, this prototype circuit offers the chance of emulating the standard STDP behavior allowing “controlled” changes for the synaptic weights. Some preliminary experimental results are reported to validate the proposed driving circuit.

A two-transistor non-ideal memristor emulator

Abstract: In this brief, the design and the experimental behavior of a memristor emulator is presented. An npn and a pnp transistor control the switching transition to the low resistance state in forward and reverse input bias, while a capacitor is responsible for the hysteresis loop. The circuit does not need external bias and in this sense it operates in a passive mode. The measured i-v characteristic exhibits a memristive hysteretic loop of Type II. Consequently, this circuit is a non-ideal memristor emulator.

Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications

Abstract: Novel memory circuits based on variable-resistance devices (such as memristors) have been recently proposed to overcome the limitations of CMOS based memories. These novel memories although based on different technologies, all share the principle of storing information as the resistance value imposed to a variable-resistance devices. Another promising application of memristors is in content-addressable memory (CAM). The study of memristor based CAM design has become increasingly important with the advent of new hybrid CMOS molecular technologies. To this end, we present a two-transistor–memristor (2T2M) bitcell for CAM design, suitable for low-power applications. The proposed circuit consists of memristors to store data and transistors as access devices, and utilizes complementary logic values at the input. We present detailed simulation based characterization (for both full match and partial match cases) and analysis, considering different word sizes of the proposed bitcells, including full parasitics, using BPTM 45-nm CMOS device models.

Boolean logic gate exploration for memristor crossbar

Abstract: Emerging technologies are under research as alternatives for next-generation VLSI circuits. One of the promising candidates is memristor due to its scalability, high integration density, non-volatility, etc. Different design styles of memristor-based logic circuits have been proposed. This paper first overviews these design styles and compares them using several criteria. Subsequently, it selects a promising candidate to explore its potential logic gate space. Thereafter, it derives control voltage constraints used to ensure correct logic gate functionality. The newly obtained logic gates are verified by SPICE simulations, and finally the performance of the memristor gates are compared with CMOS gates. The results show that the memristor gates, with reasonable technology improvements, are comparable to CMOS gates or even outperform them.

Programmable memristor emulator ASIC for biologically inspired memristive learning

Abstract: This paper details a fully programmable floating memristor (resistor with memory) emulator ASIC designed for biologically inspired memristive learning. Since real memristor is not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has a memristor emulator with conductance range from 4.88nS to 4.99µS (200KΩ to 204.8MΩ). The memristor emulator is a switched-resistor based circuit with processing performed off-chip in a FPGA. The processing has been planned to be off-chip to get the freedom of programmability of any function. This paper explains the memristor emulator and the realization of synapse functionality used in neuromorphic circuits like long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has been designed and fabricated in AMS 350nm process.

Fully digital write-in scheme for multi-bit memristive storage

Abstract: Memristors have been used in various applications, including single- and multi-bit storage units. The non-linear voltage-current relation in memristors is often seen as a problem, necessitating complex circuits and methods for a reliable write-in. In this paper, we take advantage of this phenomenon for storing more than one bit of information in a single memristor using digital bit streams. First, we demonstrate how two bits of information can be stored and read back from a single memristor unit. Then, we propose encoding schemes that can enhance the reliability of digitally writing two and three bits of data in a single memristor. To verify the reliability of this method for multi-bit data storage, we have run simulations based on the most prominent simulation models available.