Showing papers on "Microelectronics published in 2011"

Inkjet printing of single-crystal films

Abstract: Printing electronic devices using semiconducting 'ink' is seen as a promising route to cheap, large-area and flexible electronics, but the performance of such devices suffers from the relatively poor crystallinity of the printed material. Hiromi Minemawari and colleagues have developed an inkjet-based printing technique involving controlled mixing on a surface of two solutions — the semiconductor (C8-BTBT) in its solvent and a liquid in which the semiconductor is insoluble. The products of this antisolvent crystallization technique are thin semiconductor films with exceptionally high and uniform crystallinity. The use of single crystals has been fundamental to the development of semiconductor microelectronics and solid-state science1. Whether based on inorganic2,3,4,5 or organic6,7,8 materials, the devices that show the highest performance rely on single-crystal interfaces, with their nearly perfect translational symmetry and exceptionally high chemical purity. Attention has recently been focused on developing simple ways of producing electronic devices by means of printing technologies. ‘Printed electronics’ is being explored for the manufacture of large-area and flexible electronic devices by the patterned application of functional inks containing soluble or dispersed semiconducting materials9,10,11. However, because of the strong self-organizing tendency of the deposited materials12,13, the production of semiconducting thin films of high crystallinity (indispensable for realizing high carrier mobility) may be incompatible with conventional printing processes. Here we develop a method that combines the technique of antisolvent crystallization14 with inkjet printing to produce organic semiconducting thin films of high crystallinity. Specifically, we show that mixing fine droplets of an antisolvent and a solution of an active semiconducting component within a confined area on an amorphous substrate can trigger the controlled formation of exceptionally uniform single-crystal or polycrystalline thin films that grow at the liquid–air interfaces. Using this approach, we have printed single crystals of the organic semiconductor 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) (ref. 15), yielding thin-film transistors with average carrier mobilities as high as 16.4 cm2 V−1 s−1. This printing technique constitutes a major step towards the use of high-performance single-crystal semiconductor devices for large-area and flexible electronics applications.

Nanometre-scale electronics with III–V compound semiconductors

Abstract: For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Heavily doped semiconductor nanocrystal quantum dots.

Abstract: Doping of semiconductors by impurity atoms enabled their widespread technological application in microelectronics and optoelectronics. However, doping has proven elusive for strongly confined colloidal semiconductor nanocrystals because of the synthetic challenge of how to introduce single impurities, as well as a lack of fundamental understanding of this heavily doped limit under strong quantum confinement. We developed a method to dope semiconductor nanocrystals with metal impurities, enabling control of the band gap and Fermi energy. A combination of optical measurements, scanning tunneling spectroscopy, and theory revealed the emergence of a confined impurity band and band-tailing. Our method yields n- and p-doped semiconductor nanocrystals, which have potential applications in solar cells, thin-film transistors, and optoelectronic devices.

Development of hafnium based high-k materials—A review

Abstract: The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO 2 in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO 2 emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high- k materials.

Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging

Abstract: Silicon photonics is a new technology that should at least enable electronics and optics to be integrated on the same optoelectronic circuit chip, leading to the production of low-cost devices on silicon wafers by using standard processes from the microelectronics industry. In order to achieve real-low-cost devices, some challenges need to be taken up concerning the integration technological process of optics with electronics and the packaging of the chip. In this paper, we review recent progress in the packaging of silicon photonic circuits from on-CMOS wafer-level integration to the single-chip package and input/output interconnects. We focus on optical fiber-coupling structures comparing edge and surface couplers. In the following, we detail optical alignment tolerances for both coupling architecture, discussing advantages and drawbacks from the packaging process point of view. Finally, we describe some achievements involving advanced-packaging techniques.

Scalable 3D dense integration of photonics on bulk silicon.

Abstract: We experimentally show vertically stacked, multi-layer, low-temperature deposited photonics for integration on processed microelectronics. Waveguides, microrings, and crossings are fabricated out of 400°C PECVD Si3N4 and SiO2 in a two layer configuration. Waveguide losses of ~1 dB/cm in the L-band are demonstrated using standard processing and without post-deposition annealing, along with vertically separated intersections showing −0.04 ± 0.002 dB/cross. Finally 3D drop rings are shown with 25 GHz channels and 24 dB extinction ratio.

Electronics: Industry-compatible graphene transistors

Abstract: An innovative technique has been developed to manufacture graphene transistors that operate at radio frequencies and low temperatures. The process brings the devices closer to applications. See Letter p.74 Graphene, the one-atom-thick layered form of carbon, shows promise for use in high-frequency microelectronics devices. A team based at the IBM Thomas J. Watson Research Center in New York has now identified a diamond-like form of carbon, which is already well known in the semiconductor industry, as being particularly well suited for use as a substrate for graphene semiconductor devices. Graphene was grown on a copper film substrate by chemical vapour deposition (CVD) and then transferred to a wafer of diamond-like carbon. This was used to produce a high-performance graphene transistor with a cut-off frequency of 155 gigahertz at a gate length of 40 nanometres — the shortest length so far reported. This system not only achieves the highest operation speed so far for CVD-graphene transistors, but also is the smallest well-behaved transistor ever demonstrated on any graphene material.

Adhesion–delamination phenomena at the surfaces and interfaces in microelectronics and MEMS structures and packaged devices

Abstract: Physico-chemical mechanisms of adhesion and debonding at the various surfaces and interfaces of semiconductor devices, integrated circuits and microelectromechanical systems are systematically examined, starting from chip manufacturing and traversing the process stages to the ultimate finished product. Sources of intrinsic and thermal stresses in these devices are pointed out. Thin film ohmic contacts to the devices call for careful attention. The role of an adhesion layer in multilayer metallization schemes is highlighted. In packaged devices, sites facing potential risks of delamination are indicated. As MEMS devices incorporate moving parts, there are additional issues due to adhesion of suspended structures to surfaces in the vicinity, both during chip fabrication and their subsequent operation. Proper surface treatments for preventing adhesion together with design considerations for overcoming stiction pave the way to reliable functioning of these devices. Adhesion–delamination issues in microelectronics and MEMS continue to pose significant challenges to both design and process engineers. This paper is an attempt to survey the adhesion characteristics of materials, their compatibilities and limitations and look at future research trends. In addition, it addresses some of the techniques for improved or reduced adhesion, as demanded by the situation. The paper encompasses fundamental aspects to contemporary applications.

Design and Fabrication of On-Chip Coupled Inductors Integrated With Magnetic Material for Voltage Regulators

Abstract: On-chip strip-line coupled inductors integrated with magnetic material are a promising technology option to enable on-chip voltage regulators for improving power management in microelectronics. We report on design methodologies where several examples of parameter tradeoffs are presented. When considered with practical integration constraints, these result in an optimized structure. Strip-line inductors integrated with Ni80Fe20 were then fabricated, electrically characterized, and compared to models. Electrical characterization included frequency dependent measurements of effective self and mutual inductance, effective resistance, coupling coefficient, and saturation effects.

III-V compound semiconductors : integration with silicon-based microelectronics

Abstract: Part I: Basic Physical and Chemical Properties Fundamentals and the Future of Semiconductor Device Technology, M. Mastro The Challenge of III-V Materials Integration with Si Microelectronics, T. Li Part II: GaN and Related Alloys on Silicon Growth and Integration Techniques III-Nitrides on Si Substrate, J. Li, J.Y. Lin, H. Jiang, and N. Sawaki New Technology Approaches, A. Dadgar Part III: III-V Materials and Device Integration Processes with Si Microelectronics Group III-A Nitrides on Si: Stress and Microstructural Evolution, S. Raghavan and J.M. Redwing Direct Growth of III-V Devices on Silicon, T. Kazior, K.J. Herrick, and J. LaRoche Optoelectronic Device Integrated on Si, Di Liang and J.E. Bowers Reliability of III-V Electronic Devices, A.A. Immorlica, Jr. Part IV: Defect and Properties Evaluation and Characterization In Situ Curvature Measurements, Strains, and Stresses in the Case of Large Wafer Bending and Multilayer Systems, R. Clos and A. Krost X-Ray Characterization of Group III-Nitrides, A. Krost and J. Blasing Luminescence in GaN, F. Bertram Part V: Device Structures and Properties GaN-Based Optical Devices on Silicon, A. Dadgar The Conventional III-V Materials and Devices on Silicon, E.Y. Chang III-V Solar Cells on Silicon, S.A. Ringel and T.J. Grassman

Varifocal liquid lenses with integrated actuator, high focusing power and low operating voltage fabricated on 200 mm wafers

Abstract: We developed an innovative type of varifocal liquid lens actuated by electrostatic parallel plates. The 3 mm diameter lens is made of a polymer membrane that encapsulates a high permittivity liquid in a cavity on top of a glass wafer. Annular electrodes situated below the membrane and on the glass wafer form the electrostatic parallel plates actuator. By applying a voltage between the electrodes, the electrostatic actuation generated reduces the gap and pushes the liquid towards the center of the lens changing the curvature of the membrane. Compared to previous liquid lenses, very compact devices (≤6 mm × 6 mm × 0.7 mm) working at a reduced supply voltage ( −1 at 22 V RMS that can be further improved. The lenses were fabricated on 200 mm wafers using standard microelectronics processes that make our solution a promising small outline, low voltage and low cost candidate for auto-focus devices in camera phones.

Overview of recent direct wafer bonding advances and applications

Abstract: Direct wafer bonding processes are being increasingly used to achieve innovative stacking structures. Many of them have already been implemented in industrial applications. This article looks at direct bonding mechanisms, processes developed recently and trends. Homogeneous and heterogeneous bonded structures have been successfully achieved with various materials. Active, insulating or conductive materials have been widely investigated. This article gives an overview of Si and SiO2 direct wafer bonding processes and mechanisms, silicon-on-insulator type bonding, diverse material stacking and the transfer of devices. Direct bonding clearly enables the emergence and development of new applications, such as for microelectronics, microtechnologies, sensors, MEMs, optical devices, biotechnologies and 3D integration.

Semiconductor-metal transition in thin VO2 films grown by ozone based atomic layer deposition

Abstract: Vanadium dioxide (VO2) has the interesting feature that it undergoes a reversible semiconductor-metal transition (SMT) when the temperature is varied near its transition temperature at 68°C.1 The variation in optical constants makes VO2 useful as a coating material for e.g. thermochromic windows,2 while the associated change in resistivity could be interesting for applications in microelectronics, e.g. for resistive switches and memories.3 Due to aggressive scaling and increasing integration complexity, atomic layer deposition (ALD) is gaining importance for depositing oxides in microelectronics. However, attempts to deposit VO2 by ALD result in most cases in the undesirable V2O5. In the present work, we demonstrate the growth of VO2 by using Tetrakis[EthylMethylAmino]Vanadium and ozone in an ALD process at only 150°C. XPS reveals a 4+ oxidation state for the vanadium, related to VO2. Films deposited on SiO2 are amorphous, but during a thermal treatment in inert gas at 450°C VO2(R) is formed as the first and only crystalline phase. The semiconductor-metal transition has been observed both with in-situ X-ray diffraction and resistivity measurements. Near a temperature of 67°C, the crystal structure changes from VO2(M1) below the transition temperature to VO2(R) above with a hysteresis of 12°C. Correlated to this phase change, the resistivity varies over more than 2 orders of magnitude.

Controlled Polarizability of One-Nanometer-Thick Oxide Nanosheets for Tailored, High-κ Nanodielectrics

Abstract: An important challenge in current microelectronics research is the development of techniques for making smaller, higher-performance electronic components. In this context, the fabrication and integration of ultrathin high-κ dielectrics with good insulating properties is an important issue. Here, we report on a rational approach to produce high-performance nanodielectrics using one-nanometer-thick oxide nanosheets as a building block. In titano niobate nanosheets (TiNbO5, Ti2NbO7, Ti5NbO14), the octahedral distortion inherent to site-engineering by Nb incorporation results in a giant molecular polarizability, and their multilayer nanofilms exhibit a high dielectric constant (160–320), the largest value seen so far in high-κ nanofilms with thickness down to 10 nm. Furthermore, these superior high-κ properties are fairly temperature-independent with low leakage-current density (<10−7 A cm−2). This work may provide a new recipe for designing nanodielectrics desirable for practical high-κ devices.

Digital microfluidic operations on micro-electrode array architecture

Abstract: As digital microfluidics-based biochips find more applications, their complexity is expected to increase significantly due to the trend of multiple and concurrent assays on the chip. There is a pressing need to deliver a top-down design methodology that the biochip designer can leverage the same level of computer aided design support as the semiconductor industry now does. Moreover, as microelectronics fabrication technology scaling and integrated device performance improving, it is expected that these microfluidic biochips will be integrated with microelectronic components in next-generation system-on-chip designs. This paper presents a novel electrowetting-on-dielectric (EWOD) based “micro-electrode array architecture” that fosters a development path for hierarchical top-down design approach for digital microfluidics, and also allows easy integration of microfluidics and microelectronics on a single chip. In addition, this novel architecture provides a number of advantages and flexibilities over the conventional digital microfluidics such as dynamic activations of variable-sized electrodes and dynamic manipulations of multiple droplets.

Microelectronic Test Structures for CMOS Technology

Abstract: Introduction.- Test Structure Basics.- Resistors.- Capacitors.- MOSFETs.- Ring Oscillators.- High Speed Characterization.- Test Structures of SOI Technology.- Test Equipment and Measurements.- Data Analysis.

Nano-CMOS Gate Dielectric Engineering

Abstract: According to Moore’s Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devices, and fabrication processes for high-k gate dielectric materials, Nano-CMOS Gate Dielectric Engineering systematically describes how the fundamental electronic structures and other material properties of the transition metals and rare earth metals affect the electrical properties of the dielectric films, the dielectric/silicon and the dielectric/metal gate interfaces, and the resulting device properties. Specific topics include the problems and solutions encountered with high-k material thermal stability, defect density, and poor initial interface with silicon substrate. The text also addresses the essence of thin film deposition, etching, and process integration of high-k materials in an actual CMOS process. Fascinating in both content and approach, Nano-CMOS Gate Dielectric Engineering explains all of the necessary physics in a highly readable manner and supplements this with numerous intuitive illustrations and tables. Covering almost every aspect of high-k gate dielectric engineering for nano-CMOS technology, this is a perfect reference book for graduate students needing a better understanding of developing technology as well as researchers and engineers needing to get ahead in microelectronic engineering and materials science.

Interconnection elements with encased interconnects

Abstract: An interconnection element is disclosed that includes a plurality of drawn metal conductors, a dielectric layer, and opposed surfaces having a plurality of wettable contacts thereon. The conductors may include grains having lengths oriented in a direction between the first and second ends of the conductors. A dielectric layer for insulating the conductors may have first and second opposed surfaces and a thickness less than 1 millimeter between the first and second surface. One or more conductors may be configured to carry a signal to or from a microelectronic element. First and second wettable contacts may be used to bond the interconnection element to at least one of a microelectronic element and a circuit panel. The wettable contacts may match a spatial distribution of element contacts at a face of a microelectronic element or of circuit contacts exposed at a face of component other than the microelectronic element.

Low temperature wafer-level bonding for hermetic packaging of 3D microsystems

Abstract: Metallic copper–copper (Cu–Cu) thermo-compression bonding, oxide–oxide (SiO2–SiO2) fusion bonding and silicon–silicon (Si–Si) direct bonding are investigated for potential application as hermetic seal in 3D microsystem packaging. Cavities are etched to a volume of 1.4 × 10−3 cm3 in accordance with the MIL-STD-883E standard prescribed for microelectronics packaging. In the case of metal bonding, a clean Cu layer with a thickness of 300 nm and a Ti barrier layer with an underlying thickness of 50 nm are used. The wafer pair is bonded at 300 °C under the application of a bonding force of 5500 N for 1 h. On the other hand, Si–Si bonding and SiO2–SiO2 bonding are initiated at room ambient after surface activation, followed by annealing in inert ambient at 300 °C for 1 h. The bonded cavities are stored in a helium bomb chamber and the leak rate is measured with a mass spectrometer. An excellent helium leak rate below 5 × 10−9 atm cm3 s−1 is detected for all cases and this is at least ten times better than the reject limit.

Electron and hole trapping in polycrystalline metal oxide materials

Abstract: Electron and hole trapping by grain boundaries and dislocations in polycrystalline materials is important for wide ranging technological applications such as solar cells, microelectronics, photo-catalysts and rechargeable batteries. In this article, we first give an overview of the computational and methodological challenges involved in modelling such effects. This is followed by a discussion of two recent studies we have made on electron/hole trapping in wide gap insulators. The results suggest that such effects can be important for many applications which we discuss. These computationally demanding calculations have made extensive use of both the HPCx and HECToR services.

Review of laser microscale processing of silicon carbide

Abstract: A review of various laser techniques for microscale processing of SiC for microelectronics and microelectromechanical-system applications is presented. SiC is an excellent material for harsh environments due to its outstanding mechanical, thermal, and chemical properties. However, its extreme thermodynamic stability and inert properties created difficulties in conventional microfabrication methods which provided an opportunity for the exploration of laser processing as an alternative. Many aspects of laser processing of SiC are investigated across the globe using wavelengths ranging from 193 to 1064 nm and pulse widths from nanosecond to femtosecond regimes with results indicating that lasers can become successful tools for SiC microprocessing in the future. This paper is categorized into additive and subtractive laser techniques in order to facilitate a discussion of all processes used for fabricating SiC microdevices.

Toward atom probe tomography of microelectronic devices

Abstract: Atom probe tomography and scanning transmission electron microscopy has been used to analyze a commercial microelectronics device prepared by depackaging and focused ion beam milling. Chemical and morphological data are presented from the source, drain and channel regions, and part of the gate oxide region of an Intel® i5-650 p-FET device demonstrating feasibility in using these techniques to investigate commercial chips.

Polymer Based Nanodielectric Composites

Abstract: The rapid expansion of renewable energy applications demands higher efficiency and higher density energy storage and energy conversion systems (Arico et al 2005, Nourai et al 2005) Various DC-AC, AC-AC conversions are needed for solar and wind farms, while primary and secondary electrochemical devices are needed for transportation and telecommunication applications In addition, military equipment and transport have been actively moving toward more electric systems High energy density, power density and high temperature components are desired for applications such as active armor, electrochemical guns, directed energy weapons, more electric aircraft, electric launch platform, all electric warships, and so on (Sarjeant 1998, DARPA 2004) Passive components such as capacitors have been a limiting factor in full implementation of high energy density electrical systems Figure 1 shows the development history of capacitor technology Every generation of capacitors are primarily credited to the innovation and engineering of new dielectric materials The advances of such a passive component and active components have provided great foundation for future power electronics and electric power Dielectric materials are categorized into organic polymers, inorganic ceramics, filled and unfilled polymeric thin films, ceramic films and nanodielectric composites Polymer dielectric films show very high dielectric strength (>300kV/mm), lower dielectric loss ( 100) but relatively low dielectric strength ( 001), high capacitance loss (>30%) under high voltage stress (>3kV/mm) and/or piezoelectric effect associated with the ferroelectric type ceramics Thin film dielectrics are an important area leveraging either polymer or ceramic materials The thin films are usually in nanometer to submicron in thickness with very high breakdown strength But, they are primarily useful for low voltage and small size microelectronic application Scalability, reliability, cost and power level are great concerns

Ultrasonic Vibration at Thermosonic Flip-Chip Bonding Interface

Abstract: Thermosonic flip-chip (TSFC) bonding is a developing microelectronic packaging technology. To provide clear understanding of bonding process and bonding mechanism, the ultrasonic vibration at bonding interface was studied. The TSFC bonding was performed on a lab bonder, the ultrasonic vibration of tool and chip were measured by using a laser doppler vibrometer, and the effect of bonding force on chip vibration velocity harmonics was analyzed. Experimental results show that the bonding strength forming process can be divided into four stages. The abrupt “amplitude dropping” of chip vibration was observed, and could be considered as a sign of bonding strength formed. The bonding strength is formed after the bonding starts 6-8 ms. This moment can be indicated by a peak of fundamental and a ramp-up of third harmonics of chip vibration velocity. The results also show that relatively small bonding force was good for forming initial bonding strength. Then the gradually increased bonding force loading is thought to be more suitable for better bonding strength and reliability.

Microscale Controlled Electrogeneration of Patterned Mesoporous Silica Thin Films

Abstract: Mesoporous and mesostructured thin films typically prepared through the combination of low cost sol–gel processing and supramolecular chemistry are important in a wide range of applications including micro-optics and photonic devices, microelectronics, sensors, energy, environment, coatings, biomaterials, and biomicrofluidics, among others. For many of them, the full practical exploitation of these high-tech materials requires the development of micro- and nanofabrication technologies. Even if some patterning techniques have been proposed for mesostructured films (often based on extension of established procedures to mesoporous materials), controlling the important features of the local deposits (e.g., pore orientation) is still challenging. Here, we describe a novel concept to locally generate surfactant-templated silica nanostructures using a scanning electrochemical microscope. The method is based on a fine nonelectrochemical positioning of an ultramicroelectrode close to a solid support immersed in a ...

Top down nano technologies in surface modification of materials

Abstract: This article contains a broad overview of etch process as one of the most important top-down technologies widely used in semiconductor manufacturing and surface modification of nanostructures. In plasma etching process, the complexity comes from the introduction of new materials and from the constant reduction in dimensions of the structures in microelectronics. The emphasis was made on two types of etching processes: dry etching and wet etching illustrated by three dimensional (3D) simulation results for the etching profile evolution based on the level set method. The etching of low-k dielectrics has been demonstrated via modelling the porous materials. Finally, simulation results for the roughness formation during isotropic etching of nanocomposite materials as well as smoothing of the homogeneous materials have also been shown and analyzed. Simulation results, presented here, indicate that with shrinking microelectronic devices, plasma and wet etching interpretative and predictive modeling and simulation have become increasingly more attractive as a tool for design, control and optimization of plasma reactors.