Journal ArticleDOI
Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors
TLDR
In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue.Abstract:
For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.read more
Citations
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Nanometre-scale electronics with III–V compound semiconductors
TL;DR: In this article, the electron transport properties of group III-V compound semiconductors have been used for the development of the first nanometre-scale logic transistors, which is the first step towards the first IC transistors.
Journal ArticleDOI
Emerging challenges and materials for thermal management of electronics
Arden L. Moore,Li Shi +1 more
TL;DR: In this paper, a number of cubic crystals, two-dimensional layered materials, nanostructure networks and composites, molecular layers and surface functionalization, and aligned polymer structures are examined for potential applications as heat spreading layers and substrates, thermal interface materials, and underfill materials in future-generation electronics.
Journal ArticleDOI
Two-dimensional semiconductors for transistors
TL;DR: In this article, a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FET in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene.
Journal ArticleDOI
A III–V nanowire channel on silicon for high-performance vertical transistors
TL;DR: Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability.
Journal ArticleDOI
Considerations for Ultimate CMOS Scaling
TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
References
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Journal ArticleDOI
Cramming More Components Onto Integrated Circuits
TL;DR: Integrated circuits will lead to such wonders as home computers or at least terminals connected to a central computer, automatic controls for automobiles, and personal portable communications equipment as mentioned in this paper. But the biggest potential lies in the production of large systems.
Journal Article
Cramming More Components onto Integrated Circuits
TL;DR: Integrated circuits will lead to such wonders as home computers or at least terminals connected to a central computer, automatic controls for automobiles, and personal portable communications equipment as discussed by the authors. But the biggest potential lies in the production of large systems.
Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.