Showing papers on "MOSFET published in 1987"

The impact of gate-induced drain leakage current on MOSFET scaling

Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Abstract: In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.

Subbreakdown drain leakage current in MOSFET

Abstract: Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero V G in thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.

An SOI voltage-controlled bipolar-MOS device

Abstract: This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.

Integrated thermal ink jet printhead and method of manufacture

Abstract: This application discloses a thermal ink jet printhead and related integrated pulse driver circuit useful in thermal ink jet printers. This combined printhead and pulse drive integrated circuit includes a first level (5,6) of metallization compri­sing a refractory metal which is patterned to define the lateral dimension of the printhead resistor (4). A passivation layer or layers (7,8,9) are deposited atop this first level (5,6) of metalization and patterned to have an opening or openings therein for receiving a second level (10,11) of metalization. This second level (10,11) of metallization such as aluminium may then be used for electrically interconnecting the printhead resistors (4) to MOSFET drivers and the like which have been fabricated in the same silicon substrate (1) which provides suport for the printhead resistors (4). Thus, this "on-chip" driver construction enables these pulse driver transistor to be moved from external electronic circuitry to the printhead substrate.

The impact of intrinsic series resistance on MOSFET scaling

Abstract: The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

A new MOSFET-C universal filter structure for VLSI

Abstract: A new continuous-time all-MOS universal filter structure is proposed. The new structure is based on the MOSFET-C design approach. It achieves complete MOS nonlinearity cancellation and does not require the use of fully-balanced op-amps.

High‐temperature depletion‐mode metal‐oxide‐semiconductor field‐effect transistors in beta‐SiC thin films

Abstract: Depletion‐mode n‐channel metal‐oxide‐semiconductor field‐effect transistors were fabricated on n‐type β‐SiC (111) thin films epitaxially grown by chemical vapor deposition on the Si (0001) face of 6H α‐SiC single crystals. The gate oxide was thermally grown on the SiC; the source and drain were doped n+ by N+ ion implantation at 823 K. Stable saturation and low subthreshold current were achieved at drain voltages exceeding 25 V. Transconductances as high as 11.9 mS/mm were achieved. Stable transistor action was observed at temperatures as high as 923 K, the highest temperature reported to date for a transistor in any material.

Heavy-Ion-Induced, Gate-Rupture in Power MOSFETs

Abstract: A new, heavy-ion-induced, burnout mechanism has been experimentally observed in power metal-oxide-semiconductor field-effect transistors (MOSFETs). This mechanism occurs when a heavy, charged particle passes through the gate oxide region of n- or p-channel devices having sufficient gate-to-source or gate-to-drain bias. The gate-rupture leads to significant permanent degradation of the device. A proposed failure mechanism is discussed and experimentally verified. In addition, the absolute immunity of p-channel devices to heavy-ion-induced, semiconductor burnout is demonstrated and discussed along with new, non-destructive, burnout testing methods.

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Abstract: Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.

Corner-field induced drain leakage in thin oxide MOSFETs

Abstract: A new type of leakage current between drain and substrate (n-well) in thin oxide (120A-285A) n- and p-channel MOSFET's fabricated with standard CMOS n-well process is investigated. Experimental results indicate that the origin of this leakage is due to band-to-band tunneling occurring at the deep-depleted drain junction corner. It is shown that the tunneling I-V behavior can be adequately described by the analytical expression of J = B_{1}E_{si} \exp (-B_{2}/E_{si}) . The critical drain voltage corresponding to the onset of tunneling is empirically found to be 1.3 V higher in p-channel than in n-channel. Device structures with graded junctions, such as double-diffused and LDD, are also studied and demonstrated to be effective in suppressing this leakage current.

Post-Irradiation Effects in Field-Oxide Isolation Structures

Abstract: We have studied experimentally the time dependence of leakage currents in six CMOS (complementary metaloxide semiconductor) processes using LOCOS (local oxidation of silicon) isolation structures. These six process lines represent six different U. S. semiconductor companies. In their radiation response, these processes range from very hard to very soft. In the softer processes, the radiation-induced leakage currents are due to the turning on of a leakage path either under the thick field-oxide or along the transistor edge (bird's beak) region. In the hardest process, the field-oxide did not turn on, and the leakage was entirely due to subthreshold current in the gate region. These different mechanisms have qualitatively different time dependences, which we describe and discuss. We also discuss the implications of our results for hardness assurance testing.

Analysis and compensation of high-frequency effects in integrated MOSFET-C continuous-time filters

Abstract: The high-frequency operation of MOSFET-C continuoustime filters is investigated. The degradation of performance of integrators due to the effects of op-amp finite gain-bandwidth product and the distributed capacitance of the MOS transistor is characterized. A solution to minimize these effects is presented and evaluated for practical designs. Op-amp requirements for good linearity performance at high frequencies are derived. The analyses and techniques shown are verified with computer simulation and demonstrated with an experimental chip.

Two-dimensional modeling of locally damaged short-channel MOSFET's operating in the linear region

Abstract: The effect of localized damage (interface states and/or trapped charges) on the ohmic region characteristics of electrically stressed MOSFET's is analyzed using the two-dimensional (2-D) solution of Poisson's equation. The device aging induced by hot-electron injection is summarized in the formation of a narrow defective interface region whose nature, extension, and position in the channel are the parameters of our investigation. Fundamental differences are observed between the effect of interface states and that of fixed oxide charges. In addition, the channel conductance G is shown to be greatly influenced by the extension and position of the zone of defects. The correlation between the degradation of the maximum transconductance and that of the threshold voltage is modeled and demonstrated to be an important tool in the diagnosis of device degradation. The interaction between the damaged and undamaged channel regions is found to produce a transconductance overshoot that attenuates the aging effects. A negative transconductance degradation (i.e., transconductance increase) in the case of positively charged defects and an apparent amelioration of the mobility degradation factor θ in the case of localized acceptor states are two direct consequences of this effect. The errors arising from the modeling of aged devices with 1-D homogeneous analytical models are outlined.

Universal Mobility-Field Curves for Electrons and Holes in MOS Inversion Layers

Abstract: The mobility of carriers in a silicon surface inversion layer is one of the most important parameters required to accurately model and predict MOSFET device and circuit performance. It has been found that electron mobility follows a universal curve when plotted as a function of an effective normal field regardless of substrate bias, substrate doping (≤ 1017 cm−3) and nominal process variations [1]. Although accurate modeling of p-channel MOS devices has become important due to the prevalence of CMOS technology, the existence of a universal hole mobility-field relationship has not been demonstrated. Furthermore, the effect on mobility of low-temperature and rapid high-temperature processing, which are commonly used in modern VLSI technology to control impurity diffusion, is unknown.

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Abstract: Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration N off in offset-gate regions. Leakage current markedly decreases from 1 × 10-9to 2 × 10-11A at V D = 10 V as N off is varied from 1 × 1018to 1 × 1017cm-3. A maximum ON/OFF current ratio of 108is obtained at 1 × 1017cm-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.

Mosfet switch with an inductive load

Abstract: The voltage peaks occuring upon disconnection of inductive loads are normally attenuated by a by-pass diode connected in parallel with the load. The driving countervoltage is thereby limited to the value of the forward voltage drop of the diode. For a power MOSFET with a source-side inductive load, the driving countervoltage is increased by placing a series connection of an additional MOSFET and a Zener diode between the gate of the power MOSFET and the connection of the load which is remote from the power MOSFET. The driving countervoltage at the source now becomes the Zener voltage plus the occuring gate-source voltage of the power MOSFET.

Anomalous subthreshold current—Voltage characteristics of n-channel SOI MOSFET's

Abstract: The abnormally high slopes of the subthreshold current-voltage characteristics exhibited by n-channel silicon-on-insulator (SOI) MOSFET's are experimentally related to defect density (off-state leakage current) as well as drain voltage and channel length, and a theoretical physical description of the measured relations is presented and supported. The anomalous subthreshold behavior is attributed analytically to the (floating) body effect due to charging (biasing) by impact ionization at the drain.

Scattering of silicon inversion layer electrons by metal/oxide interface roughness

Abstract: The roughness at the metal/gate oxide interface of metal‐oxide‐semiconductor field‐effect transistor (MOSFET) has been modeled. The mobility of electrons inside the channel of the MOSFET, limited by the scattering resulting from this roughness, has been calculated. The magnitude of this scattering mechanism is a strong function of the oxide thickness. For a MOSFET with very thin gate oxide (<100 A), this limiting mobility may become comparable to the total mobility, and the scattering of electrons by the remote interface roughness can no longer be ignored.

Resonant rectifier circuit

Abstract: A self-oscillating power converter utilizes a MOSFET power transistor switch with its output electrode coupled to a tuned network that operatively limits the voltage waveform across the power switch to periodic unipolar pulses. The transistor switch may be operated at a high radio frequency so that its drain to gate interelectrode capacitance is sufficient to comprise the sole oscillatory sustaining feedback path of the converter. A reactive network which is inductive at the operating frequency couples the gate to source electrodes of the transistor switch and includes a variable capacitance as a means of adjusting the overall reactance, and hence the converter's switching frequency in order to provide voltage regulation. A resonant rectifier includes a tuned circuit to shape the voltage waveform across the rectifying diodes as a time inverse of the power switch waveform. The input resistance of the rectifier is controlled so that it is invariant to frequency change within the switching frequency range of the converter but inversely proportional to the load resistance.

MOSFET behavior and circuit considerations for analog applications at 77 K

Abstract: We present an investigation into the behavior of silicon MOS transistors and analog circuits operated at liquid-nitrogen temperature (LNT). Simple scaling rules are used to predict the LNT performance of CMOS operational amplifier circuits designed for room-temperature operation. Measurements show that unity gain frequency and slew rate can be improved by the same amount as the mobility increase with no loss of stability if bias currents are properly controlled. We also show that room-temperature CMOS amplifier circuits can be redesigned for 77-K operation by reducing channel widths and compensation capacitor area, giving performance equal in most respects to that of unscaled circuits at room temperature. However, 1/f noise is degraded by such redesign. Similar considerations of NMOS amplifiers show that such circuits do not benefit greatly from operation at liquid-nitrogen temperature. To aid in studying the temperature dependence of the sheet resistance of diffused resistors, a computer program was developed based on available models for bulk mobility and carrier freeze-out. Accurate predictions require a temperature dependence for lattice scattering that differs from previously reported values.

An improved method of MOSFET modeling and parameter extraction

Abstract: A method is presented to accurately determine MOSFET modeling parameters from a single linear region (V DS BT/q )I D - V GS measurement based on the operation of a single transistor in the strongly inverted regime. The intrinsic values of the surface scattering parameter θ s and the transistor gain β 0 may be separated from the series resistance R s and drain bias V DS effects while including band bending beyond the 2φ F point. The mobility (excluding surface scattering effects), threshold voltage, bulk doping, and flat-band voltage are also determined.

High-speed BiCMOS technology with a buried twin well structure

Abstract: A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (f T = 4 GHz) and small size (500 µm2) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Abstract: Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Abstract: Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.

Vertical MOSFET having a proof structure against puncture due to breakdown

Abstract: A vertical MOSFET having a reduced drain to source resistance is described as comprising a well region which are formed with a suitable distance from a high resistivity drain substrate and in contact with a source electrode. Undesirable parasitic bipolar transistor action can be prevented.

Semi-empirical model for the threshold voltage of a double implanted MOSFET and its temperature dependence

Abstract: A simple and accurate semi-empirical model for the threshold voltage of a small geometry double implanted enhancement type MOSFET, especially useful in a circuit simulation program like SPICE, has been developed. The effect of short channel length and narrow width on the threshold voltage has been taken into account through a geometrical approximation, which involves parameters whose values can be determined from the curve fitting experimental data. A model for the temperature dependence of the threshold voltage for the implanted devices has also been presented. The temperature coefficient of the threshold voltage was found to change with decreasing channel length and width. Experimental results from various device sizes, both short and narrow, show very good agreement with the model. The model has been implemented in SPICE as a part of the complete d.c. model.

CMOS digital-to-analog converter circuitry

Abstract: A CMOS digital-to-analog converter includes a modified R-2R resistive ladder network connected to 16 pairs of bit switches responsive to the various digital inputs to produce an internal analog voltage representative of the digital input. Each pair of bit switches includes an N-channel MOSFET and a P-channel MOSFET. The on resistance of the P-channel MOSFET is adjusted to precisely match that of the N-channel MOSFET by driving the gate of each P-channel MOSFET with the output of a CMOS inverter referenced between VCC and a reference voltage that is adjusted to cause the on resistances of a P-channel "monitor" MOSFET and an N-channel "monitor" MOSFET to be equal. A reference voltage is generated by a circuit that generates a temperature-invariant source current from a VBE difference between first and second transistors, causes part of it to flow through first, second, and third resistors, the third resistor having a voltage across it established by the VBE voltage of a transistor and having a predetermined negative temperature coefficient, the second and third resistors being composed of nichrome, the first resistor being lightly doped P-type material the resistance of which has a positive temperature coefficient.

Vertical depletion-mode j-MOSFET

Abstract: A vertical j-MOSFET useful as a power transistor includes a two-dimensional array of square cells in which a small fraction of the cells are replaced by a double-junction sink useful for collecting the minority carriers in the channel regions that normally will accumulate at each interface of the gate electrode and channel region.

Effect of oxide field on hot‐carrier‐induced degradation of metal‐oxide‐semiconductor field‐effect transistors

Abstract: While the substrate current is a useful tool for extrapolating metal‐oxide‐semiconductor field‐effect transistor lifetime from accelerated stressing data, the substrate current can vary significantly during a constant‐voltage stress test. We have studied device degradation using a constant‐field method. The critical electron energy for device degradation is found to be 3–6 eV, depending on the oxide electric field. These values are 50% higher than those reported elsewhere.