Showing papers on "Phase detector published in 2013"

Advantages and Challenges of a Type-3 PLL

Abstract: A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions.

A Novel Phase-Locked Loop Based on Frequency Detector and Initial Phase Angle Detector

Abstract: This paper proposes a new three-phase software phase-locked loop (PLL) that operates fast and accurately in unbalanced, polluted, and frequency deviating circumstances. The proposed PLL consists of a frequency detector and an initial phase angle detector. In the synchronous reference frame, the initial phase angle detector tracks a ramp phase angle, which is generated from frequency deviation of the inputs, with steady error. This detection error is utilized to estimate the actual grid frequency. Frequency adaptive moving average filters (MAFs) are applied in this new PLL to eliminate noises, harmonics, and negative sequence components. In this paper, the effect of discrete sampling on the MAFs is analyzed, and a linear interpolation is employed to enhance the performances of the MAFs. The stability of the proposed PLL is also analyzed, a sufficient stability condition is identified, and the design procedures of the control parameters are also presented. Simulations and experiments verify the performances of the novel PLL.

Clock recovery circuit

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

System and method for measuring the phase of a modulated optical signal

Abstract: The invention is related to phase detection in lidar systems using single photon detectors (SPDs). The frequency at which the SPDs are time gated is related to but not an integer multiple of the frequency of the transmitted optical pulses. Each return optical pulse arrives with a particular temporal position with respect to the nearest gate, and thus is detected with a related detection efficiency. The SPD output can be segmented into multiple time-multiplexed signals whose relative detection efficiency reveals the phase of the optical return pulses, and no such phases have negligible detection efficiency for all the time-multiplexed signals. To mitigate the impact of afterpulsing and other saturation effects, when a first optical pulse is detected with high detection efficiency the next optical pulse that is detected with high detection efficiency is separated by a time period about equal to or greater than the detector dead time.

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

Abstract: This paper introduces a novel architecture of digital PLL. The goal of this architecture is to reach low jitter, fractional operation, and FSK modulation capability with low architecture complexity for small area, low power, and minimal design effort. The architecture is based on the bang-bang phase detector, so that usage of time-to-digital-converter circuits is avoided, with no need for any background calibration. The key enabling blocks are a phase interpolator-based exact fractional frequency divider, and a multi-output bang-bang phase detector. The prototype implemented in 130 nm reaches 1-psrms absolute jitter while operating in integer mode and 1.9 psrms absolute jitter while operating in full fractional mode, with an output frequency of 1 GHz and reference frequency of 25 MHz, consuming 7.4 mW from a supply of 1.3 V. FSK modulation of the 1 GHz carrier up to 300 kbps with a frequency deviation of ±150 kHz is also implemented and measured .

FPGA Implementation of the Generalized Delayed Signal Cancelation—Phase Locked Loop Method for Detecting Harmonic Sequence Components in Three-Phase Signals

Abstract: Fundamental-frequency and harmonic positive- and negative-sequence components detection is an important task for implementing power converters for renewable energy systems, uninterruptible power supplies, active power filters, dynamic voltage restorers, and also for power systems protection relays. Detection techniques of this kind are generally implemented in digital signal processor (DSP) with the execution time limited by the sampling period. The computational effort of the control algorithm can considerably increase the execution time, due to the sequential nature of processing in DSP. A promising technique for sequence components separation of three-phase signals is the so called the generalized delayed signal cancelation-phase locked loop (GDSC-PLL). Field programmable gate array's (FPGA's) capacity of exploring the parallelism of operations present in the GDSC-PLL is demonstrated in this paper through the mapping of this technique directly in hardware, allowing for a much shorter execution time than in DSP. The proposed architecture is presented, and the efficient detection of the fundamental-frequency positive-sequence with FPGA is demonstrated, with the obtained results compared with a traditional DSP implementation. In particular, the advantages and possibilities of the use of FPGA are demonstrated in comparison with the DSP. For this comparison, a metric for evaluating the capacity of complexity increase in application algorithms is proposed.

Self injection locked phase locked looped optoelectronic oscillator

Abstract: Aspects of the disclosure relate generally to a circuit (100) for sustaining an radio frequency (RF) modulated optical signal. The circuit may comprise a self injection locking component (107) having a fiber optic delay line (130) over which a portion of the optical signal propagates. The circuit may also comprise a self phase locked loop component (109) having at least two fiber optic cables (120, 140) having different lengths and over which another portion of the optical signal propagates and a phase detector (150) coupled to the at least two fiber optic cables and configured to determine a phase difference between the signals propagating over one of the respective fiber optic cables. The circuit may further comprise a voltage controlled oscillator (110) configured to generate a stable oscillating signal in response to signals generated by each of the self injection locking and self phase locked loop components, the stable oscillating signal being configured to sustain the optical signal.

Ultralow Phase Noise Microwave Generation From Mode-Locked Er-Fiber Lasers With Subfemtosecond Integrated Timing Jitter

Abstract: We demonstrate ultralow phase noise 10-GHz microwave signal generation from a free-running mode-locked Er-fiber laser with -142- and -157-dBc/Hz single-sideband absolute phase noise at 10- and 100-kHz offset frequencies, respectively. The absolute RMS timing jitter is 1.5 fs when integrated from 1-kHz to 5-GHz (Nyquist frequency) offset frequency. In the 10-kHz to 10-MHz integration bandwidth typically used for microwave generators, the RMS integrated jitter is 0.49 fs. The Er-fiber laser is operated in the stretched-pulse regime at close-to-zero dispersion to minimize the phase noise of extracted microwaves. In order to suppress the excess phase noise in the optical-to-electronic conversion process, we synchronize a low-noise voltage-controlled oscillator to the fiber laser using a fiber Sagnac-loop-based optical-microwave phase detector.

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing

Abstract: A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1, 2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented.

Distance measuring system

Abstract: A light emission reference signal, the timing of which is adjusted by a first delay time control circuit, is input as a timing adjustment signal to a light emitter driver The light emission reference signal, which is delayed by a second delay time control circuit, is output as an offset signal The offset signal and a light emission timing signal from the light emitter driver are input to a timing correction phase comparator, and a phase comparison result is output from the timing correction phase comparator The phase comparison result is input to a timing correction control logic circuit, and a delay adjusting signal based on the phase comparison result is output from the timing correction control logic circuit The delay adjusting signal is input to the first delay time control circuit, whereby the timing of the light emission reference signal is adjusted

Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

Abstract: This paper describes an accurate, yet analytical method to predict the key characteristics of a bang-bang controlled timing loop: namely, the jitter transfer (JTRAN), jitter generation (JG), and jitter tolerance (JTOL). The analysis basically derives a linearized model of the system, where the bang-bang phase detector is modeled as a set of two linearized gain elements and an additive white noise source. This phase detector (PD) model is by far the most extensive one in literature, which can correctly estimate the effects of random jitter, transition density, and finite loop latency on the loop characteristics. The described pseudo-linear analysis assumes the presence of random jitter at the PD input and the minimum jitter necessary to keep the linear model valid is derived, based on a describing function analysis and Nyquist stability analysis. The presented analysis re-confirms the findings of prior theories and provides theoretical basis to the prior empirically-drawn equations, such as those for the quantization noise power and the gain reduction in presence of a finite loop delay. The predictions based on the presented analysis match well with the results from time-accurate behavioral simulations.

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

Abstract: A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.

Modeling and Implementation of an All Digital Phase-Locked-Loop for Grid-Voltage Phase Detection

Abstract: In this paper, a novel all digital phase-locked-loop (ADPLL) is proposed for the phase detection of power grid voltage. The proposed ADPLL features wide track-in range and fast pull-in time, and it can be easily integrated into the digital controller with low cost. The nonlinear model of such digital system is derived from the operation principle of the ADPLL and the linearized model is then obtained to evaluate the steady and dynamic performance due to the nonlinear and discrete property. Compared with the conventional DPLL, the proposed ADPLL has almost no steady state phase error when the frequency of the input signal deviates from the center frequency. Moreover, the tracking speed is highly improved. In contrast with other ADPLLs, the proposed one employs the loop filter with proportional-Integral (PI) structure, which can help to eliminate the steady state error excited by high-order disturbances or noise. As a result, a low system clock or sampling frequency is enough to get a satisfactory performance, which is an attractive advantage for the low cost applications. Simulation and experimental results verify the analysis and the effectiveness of the ADPLL.

Frequency comb-based microwave transfer over fiber with $7 \times 10^{-19}$ instability using fiber-loop optical-microwave phase detectors

Abstract: We demonstrate a remote microwave/radio-frequency (RF) transfer technique based on the stabilization of a fiber link using a fiber-loop optical-microwave phase detector (FLOM-PD). This method compensates for the excess phase fluctuations introduced in fiber transfer by direct phase comparison between the optical pulse train reflected from the remote site and the local microwave/RF signal using the FLOM-PD. This enables sub-fs resolution and long-term stable link stabilization while having wide timing detection range and less demand in fiber dispersion compensation. The demonstrated relative frequency instability between 2.856-GHz RF oscillators separated by a 2.3-km fiber link is $7.6 \times 10^{-18}$ and $6.5 \times 10^{-19}$ at 1000 s and 82500 s averaging time, respectively.

Suppression of amplitude-to-phase noise conversion in balanced optical-microwave phase detectors

Abstract: We demonstrate an amplitude-to-phase (AM-PM) conversion coefficient for a balanced optical-microwave phase detector (BOM-PD) of 0.001 rad, corresponding to AM-PM induced phase noise 60 dB below the single-sideband relative intensity noise of the laser. This enables us to generate 8 GHz microwave signals from a commercial Er-fibre comb with a single-sideband residual phase noise of –131 dBc Hz–1 at 1 Hz offset frequency and –148 dBc Hz–1 at 1 kHz offset frequency.

Delay-locked loop with dynamically biased charge pump

Abstract: A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

A Highly Sensitive and Low-Cost Sagnac Loop Based Pressure Sensor

Abstract: A pressure sensor based on Sagnac loop using polarization-maintaining photonic crystal fiber operating at 850 nm with much extended measuring range is experimentally demonstrated We propose a frequency and phase detection technique to enable much extended measurement range comparing with previously proposed schemes The scheme gives a linear relationship between phase and pressure variation Experimental results agree well with theoretical predications The study also shows that operating at 850 nm improves pressure sensitivity by about three times compared with sensors operating at 1550 nm It enables the use of low-cost and high-speed charge-coupled device interrogator for measurement

A 0.18- $\mu$ m CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration

Abstract: This letter presents a 0.18 μm CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than -63 dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18-5.32 GHz and 5.74-5.82 GHz.

A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of $-$ 252.5 dB

Abstract: A subharmonically injection-locked all-digital phase-locked loop (ADPLL) is presented to achieve both low power and low phase noise simultaneously. This ADPLL uses a bang-bang phase detector to maintain the phase locking without a time-to-digital converter, and the dividers can be disabled to reduce the power. In addition, a subharmonically injection-locked technique is used to achieve a low phase noise. This ADPLL is fabricated in a 40-nm complementary metal-oxide-semiconductor technology. Its power consumption is 3.661 mW for a supply voltage of 1.1 V. The measured phase noise is equal to -122.33 dBc/Hz at an offset frequency of 1 MHz. The integrated root-mean-square jitter is 123.4 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure of merit is equal to -252.5 dB.

A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor

Abstract: This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5× to 8× of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-μm CMOS process occupies an active area of 0.27 mm2 and consumes 15.56 mA.

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

Abstract: A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-μm CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm. The reference spur of the proposed PLL is measured to be -80 dBc/-74 dBc and an in-band phase noise of -103 dBc/Hz at 100 kHz offset is achieved.

Bridging the Gap Between Kalman Filter and Wiener Filter in Carrier Phase Tracking

Abstract: Data-aided carrier recovery based on phase-lock loop (PLL) is a popular scheme for tracking the phase of an incoming carrier affected by phase noise. Optimum tracking is achieved by a Kalman filter, that, with multilevel quadrature amplitude modulation (QAM), is implemented by a PLL with variable loop gain. This letter shows that a PLL with fixed gain achieves a performance that is close to the optimal one provided that the phase detector is optimized. Monte Carlo simulations for the mean-square phase error and the symbol error rate of a 256-QAM constellation are provided to validate the analysis.

Techniques for varying a periodic signal based on changes in a data rate

Abstract: A circuit includes phase detection, frequency adjustment, sampler, and control circuits. The phase detection circuit compares phases of first and second periodic signals to generate a control signal. The frequency adjustment circuit adjusts a frequency of the second periodic signal and a frequency of a third periodic signal based on the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The control circuit adjusts the frequency of the third periodic signal based on the data signal changing from a first data rate to a second data rate while maintaining the frequency of the second periodic signal constant. The control circuit adjusts the frequency of the second periodic signal and the frequency of the third periodic signal based on the data signal changing from the second data rate to a third data rate.

Modified Gardner phase detector for Nyquist coherent optical transmission systems

Abstract: We present a novel timing recovery scheme based on a Gardner phase detector performing excellently in spectrally efficient Nyquist coherent optical systems. Good clock tone performance is obtained for QAM modulation formats and roll-off factor (ROF) values close to 0.

A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO

Abstract: An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.

Digital phase detector

Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.

A 38 Gb/s to 43 Gb/s Monolithic Optical Receiver in 65 nm CMOS Technology

Abstract: A scaled 40 Gb/s optical receiver incorporating a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery (CDR), and a 1:4 demultiplexer was proposed in 65 nm CMOS technology. The TIA employs a regulated cascode structure to achieve low input resistance and a stable dc operating point, whereas the LA adopts the third-order interleaving active feedback technique to obtain greater bandwidth and flatter frequency response. A 10 GHz LC-based voltage controlled oscillator with a ring structure that generates eight phases is presented. A quarter-rate phase detector in the CDR samples the 40 Gb/s input data, which are retimed and demultiplexed into four sets of 10 Gb/s output data. Experimental results show that the recovered clock exhibits a phase noise of -112.39 dBc/Hz@10 MHz from a carrier frequency of 10 GHz, in response to 231-1 PRBS input. The retimed and demultiplexed data exhibit a peak-peak jitter of 4.46 ps and an RMS jitter of 1.18 ps. The core circuit of the receiver consumes 160 mW from a 1.2 V supply.

System and method for synchronizing local oscillators

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.