Showing papers on "Phase noise published in 2001"

A filtering technique to lower LC oscillator phase noise

Abstract: Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed.

Concepts and methods in optimization of integrated LC VCOs

Abstract: Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-/spl mu/m MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results.

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

Abstract: This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

Abstract: A highly integrated 175-GHz 035-/spl mu/m CMOS transmitter is described The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 13/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal The prototype consumed 151 mA from a 3-V supply A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance

Understanding the effects of phase noise in orthogonal frequency division multiplexing (OFDM)

Abstract: Phase noise must be carefully considered when designing an OFDM-based communication system since an accurate prediction of the tolerable phase noise can allow the system and RF engineers to relax specifications. This paper analyzes the performance of OFDM systems under phase noise and its dependence on the number of sub-carriers both in the presence and absence of a phase correction mechanism. Besides some practical results are provided so as to give some insight into the phase noise spectral specifications that should be required of the local oscillator.

Mining partially periodic event patterns with unknown periods

Abstract: Periodic behavior is common in real-world applications. However in many cases, periodicities are partial in that they are present only intermittently. The authors study such intermittent patterns, which they refer to as p-patterns. The formulation of p-patterns takes into account imprecise time information (e.g., due to unsynchronized clocks in distributed environments), noisy data (e.g., due to extraneous events), and shifts in phase and/or periods. We structure mining for p-patterns as two sub-tasks: (1) finding the periods of p-patterns and (2) mining temporal associations. For (2), a level-wise algorithm is used. For (1), we develop a novel approach based on a chi-squared test, and study its performance in the presence of noise. Further we develop two algorithms for mining p-patterns based on the order in which the aforementioned sub-tasks are performed: the period-first algorithm and the association-first algorithm. Our results show that the association-first algorithm has a higher tolerance to noise; the period-first algorithm is more computationally efficient and provides flexibility as to the specification of support levels. In addition, we apply the period-first algorithm to mining data collected from two production computer networks, a process that led to several actionable insights.

Ofdm pilot tone tracking for wireless lan

Abstract: A pilot phase tracking loop for an OFDM receiver including a phase rotator receiving an incoming signal, a fast Fourier transform coupled to a phase rotator output, and a pilot phase error metric including a discrete Fourier transform portion coupled to the phase rotator output. The pilot phase error metric determines a phase error estimate associated with a received OFDM symbol, e.g., a data symbol, from the phase rotator output. A loop filter is coupled to the pilot phase error metric output and an oscillator is coupled to the loop filter output. The oscillator output is coupled to the phase rotator to adjust the phase of subsequent OFDM symbols of the incoming signal. Phase noise introduced by a radio portion of the OFDM receiver and OFDM transmitter is reduced by the baseband portion of the OFDM receiver improving OFDM signal tracking under poor SNR conditions.

A new direct millimeter-wave six-port receiver

Abstract: A new direct-conversion wide-band (23-31 GHz) six-port receiver is proposed suitable for millimeter-wave integrated system design. This new hardware receiver is found to be robust, rugged, low cost, and suitable for use in broad-band wireless mass-market QPSK communications. The prototype circuits are fabricated to validate this new concept with our miniaturized hybrid microwave integrated-circuit technology and the proposed receiver topology is also suitable for monolithic-microwave integrated-circuit fabrication. This application-specific integrated receiver is designed on the basis of a wide-band six-port junction and other analogical circuits in the form of a simple multichip module. Bit-error-rate measurements and simulation results are shown and discussed in the presence of noise, adjacent signal interference, local-oscillator (LO) phase shift, and LO phase noise. The maximum bit rate is fundamentally limited by the speed of the video and decoder circuits. Nevertheless, several hundred megabits per second can be achieved at low cost.

High-dynamic-range laser amplitude and phase noise measurement techniques

Abstract: We describe techniques for making sensitive and high-dynamic-range measurements of laser amplitude and envelope phase noise (timing jitter) in the frequency domain at the shot-noise limit. Examples of amplitude noise measurements on continuous-wave argon-ion and diode-pumped solid-state lasers used for pumping a femtosecond Ti:sapphire laser are presented. Amplitude and phase noise measurements for the Ti:sapphire laser are also presented, showing correlation between pump laser amplitude modulation (AM) spectra and the resulting AM and phase noise. Characteristics of the measurement system components are discussed, along with examples of the impact these have on achieving reliable high-dynamic-range measurement capability.

A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator

Abstract: A 900-MHz two-stage CMOS voltage-controlled ring oscillator (VCO) with good phase-noise performance is presented. Implemented in a 0.5-/spl mu/m CMOS technology and at 2.5-V supply voltage, the VCO has a wide operating frequency range from 661.5 MHz to 1.27 GHz with a peak VCO gain (K/sub VCO/) of -630 MHz/V. At 900 MHz, the phase noise of the VCO is -105.5 dBc/Hz at 600-kHz frequency offset with low power consumption of 15.4 mW. The gain and phase mismatches are less than 0.25 dB and 0.5/spl deg/, respectively, which corresponds to an image rejection of better than 31 dB. The chip area is only 125/spl times/102 /spl mu/m/sup 2/.

Silicon-based distributed voltage-controlled oscillators

Abstract: Distributed voltage-controlled oscillators (DVCOs) are presented as a new approach to the design of silicon VCOs at microwave frequencies. In this paper, the operation of distributed oscillators is analyzed and the general oscillation condition is derived, resulting in analytical expressions for the frequency and amplitude. Two tuning techniques for DVCOs are demonstrated, namely, the inherent-varactor tuning and delay-balanced current-steering tuning. A complete analysis of the tuning techniques is presented. CMOS and bipolar DVCOs have been designed and fabricated in a 0.35-/spl mu/m BiCMOS process. A 10-GHz CMOS DVCO achieves a tuning range of 12% (9.3-10.5 GHz) and a phase noise of -103 dBc/Hz at 600 kHz offset from the carrier. The oscillator provides an output power of -4.5 dBm without any buffering, drawing 14 mA of dc current from a 2.5-V power supply. A 12-GHz bipolar DVCO consuming 6 mA from a 2.5-V power supply is also demonstrated. It has a tuning range of 26% with a phase noise of -99 dBc/Hz at 600 kHz offset from the carrier.

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop

Abstract: A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K/sub VCO/) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply.

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

Abstract: This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.

Numerical modeling of intensity and phase noise in semiconductor lasers

Abstract: A self-consistent numerical approach is demonstrated to analyze intensity and phase noise in semiconductor lasers. The approach takes into account the intrinsic fluctuations of the photon number, carrier number, and phase. A new systematic technique is proposed to generate the Langevin noise sources that derive the laser rate equations keeping their cross-correlations satisfied. The simulation is applied to AlGaAs lasers operating in a single mode. The time-varying profiles of the fluctuating photon and carrier numbers and the instantaneous shift of the oscillating frequency are presented. Statistical analysis of the intensity and phase fluctuations is given. The frequency spectra of intensity and phase noise are calculated with help of the fast Fourier transform. The importance of taking into account the carrier number noise source and its cross-correlation with the noise source on the phase is examined by comparing our results with those by conventional methods.

Jitter measuring device and method

Abstract: A signal under measurement is transformed into a complex analytic signal using a Hilbert transformer and an instantaneous phase of this analytic signal is estimated. A linear phase is subtracted from the instantaneous phase to obtain a phase noise waveform. The phase noise waveform is sampled in the proximity of a zero crossing point of a real part of the analytic signal. A differential waveform of the sample phase noise waveform is calculated to obtain a differential phase noise waveform. An RMS jitter is obtained from the phase noise waveform, and a peak-to-peak jitter is obtained from the phase noise waveform.

Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO

Abstract: A switched resonator concept which allows better trade-off between phase noise and power consumption is demonstrated using a dual band VCO. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and 123 dBc/Hz at a 600-KHz offset and 16-mW power consumption. Compared to a single band 1.8 GHz VCO, the dual-band VCO has almost the same phase noise and power consumption.

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

Abstract: More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers

Abstract: We implemented prescalers that can operate up to 2.8-GHz by exploiting the injection locking phenomena in differential CMOS ring oscillators. We tested a 5-stage, 1-GHz injection-locked modulo-8 prescaler fabricated in a 0.24-/spl mu/m CMOS technology that consumes 350 /spl mu/W of power and occupies 0.012 mm/sup 2/ of die area. The locking range is 20 MHz and the locked phase noise is -110 dBc/Hz @ 100 kHz. A 2.8-GHz, 3-stage, modulo-4 divider is also presented.

Analytical modeling and simulation of phase noise interference in OFDM-based digital television terrestrial broadcasting systems

Abstract: This paper deals with the problem of modeling of phase noise in OFDM systems and the impact it may have on the bit error rate performance of such systems subject to a number of system variables and to a number of channel conditions which may be encountered when such systems are deployed for certain applications such as high speed wireless LANs and Digital Television Terrestrial Broadcasting (DTTB). The phase noise processes, the sources of which are the transmitter's and receiver's local oscillator, are modeled using what is believed to be commercially realizable phase noise masks. Such masks represent the long-term averaged power spectral densities of the local oscillator output signal.

Phase-map measurements by interferometry with sinusoidal phase modulation and four integrating buckets

Abstract: Phase-shifting interferometry based on the integrating-bucket technique with sinusoidal phase modulation is studied theoretically and demonstrated experimentally to obtain phase maps from double-beam interferometers. The method uses four frames obtained by integration of the time-varying intensity in an interference pattern during the four quarters of the modulation period. An optimum sinusoidal phase modulation is found to minimize the effect of the additive noise. The absolute accuracy of the phase measurements is discussed. Possible applications of the method are demonstrated with two interference microscopes with which the phase modulation is achieved by sinusoidal oscillation of a mirror attached to a piezoelectric transducer and by sinusoidal birefringence modulation with a photoelastic modulator. In both experimental arrangements, phase images can be produced in real time at a rate of several hertz. Noise measurements are reported and compared with theory.

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

Abstract: This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-/spl mu/m digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8/spl times/0.4 mm/sup 2/.

Fully integrated 5.35-GHz CMOS VCOs and prescalers

Abstract: Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-/spl mu/m CMOS process. One VCO uses p/sup +//n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p/sup +//n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming /spl sim/7 mW power at V/sub DD/=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V/sub DD/ and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V/sub DD/=2.5 V.

Optimum Nyquist windowing in OFDM receivers

Abstract: Conventional orthogonal frequency-division multiplexing receivers disregard the guard interval in channels with small dispersion even though its unconsumed portion can be exploited for improved demodulation by applying a Nyquist-shaped window in the receiver. The transmitter does not need to be modified, subcarrier orthogonality in the receiver is preserved, and the receiver discrete Fourier transform size can be retained. Windowing can mitigate the joint effect of additive noise and intercarrier interference among subcarriers caused by the carrier frequency offset. A closed solution for optimum window coefficients suited to this scenario is derived.

Analysis of 1/f noise in switched MOSFET circuits

Abstract: Analysis of 1/f noise in MOSFET circuits is typically performed in the frequency domain using the standard stationary 1/f noise model. Recent experimental results, however, have shown that the estimates using this model can be quite inaccurate especially for switched circuits. In the case of a periodically switched transistor, measured 1/f noise power spectral density (psd) was shown to be significantly lower than the estimate using the standard 1/f noise model. For a ring oscillator, measured 1/f-induced phase noise psd was shown to be significantly lower than the estimate using the standard 1/f noise model. For a source follower reset circuit, measured 1/f noise power was also shown to be lower than the estimate using the standard 1/f model. In analyzing noise in the follower reset circuit using frequency-domain analysis, a low cutoff frequency that is inversely proportional to the circuit on-time is assumed. The choice of this low cutoff frequency is quite arbitrary and can cause significant inaccuracy in estimating noise power. Moreover, during reset, the circuit is not in steady state, and thus frequency-domain analysis does not apply. This paper proposes a nonstationary extension of the standard 1/f noise model, which allows us to analyze 1/f noise in switched MOSFET circuits more accurately. Using our model, we analyze noise for the three aforementioned switched circuit examples and obtain results that are consistent with the reported measurements.

Offset phase locking of Er,Yb:glass laser eigenstates for RF photonics applications

Abstract: An optical source of microwaves with very low phase noise for communications and radar systems is realized and tested. It is obtained by dual-frequency operation of a diode pumped Er,Yb:glass laser. An electrooptic crystal inserted inside the resonator permits both to tune the frequency difference between orthogonally polarized eigenstates, and to turn the laser into a voltage controlled oscillator. An optical phase-locked loop is then implemented in the GHz range, resulting in a measured instrument limited 3 dB-linewidth of 10 Hz. The phase noise is shown to be -100 dBc/Hz at 10-kHz offset.

Phase controlled oscillator

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Noise in phase-locked loops

Abstract: Jitter and phase noise properties of phase-locked loops (PLL) are analyzed, identifying various forms of jitter and phase noise in PLLs. The effects of different building blocks on the jitter and phase noise performance of PLLs are demonstrated through a parallel analytical and graphical treatment of noise evolution in the phase-locked loop.

Observation of twin-beam-type quantum correlation in optical fiber.

Abstract: We report generation of pulsed twin beams of light through optical parametric amplification in a fiber Sagnac loop. By pumping the Sagnac loop with picosecond pulses at a wavelength near the zero-dispersion wavelength of the fiber, we achieve phase-matched nondegenerate four-wave mixing with gain. For a gain of 2.2, the intensity noises of the amplified signal and the generated idler (conjugate) pulses are found to be correlated by 5.0 dB, and the subtracted noise drops below the shot-noise limit by 1.1 dB (2.6 dB when corrected for losses). We have investigated the gain dependence of the quantum-noise reduction as well as of the intensity noises of the amplified signal and idler pulses. As the gain increases, we observe the onset of excess noise on the idler pulses.

A 10-MHz Micromechanical Resonator Pierce Reference Oscillator for Communications

Abstract: A modified Pierce circuit topology has been used to first demonstrate a 9.75 MHz μmechanical resonator reference oscillator, then to assess the ultimate frequency stability of such an oscillator via accurate measurement of its close-to-carrier phase noise, which seems to exhibit an unexpected 1/f 3 dependence that limits the phase noise to −80 dBc at a 1 kHz offset from the carrier—a value that must be improved before use in most communications applications. Through theoretical analysis, this 1/f 3 dependence seems to derive from aliasing of active circuit 1/f noise onto the carrier caused by nonlinearity in the capacitive transducer of the μmechanical resonator.

An approach to consistent jitter modeling for various jitter aspects and measurement methods

Abstract: Timing jitter, period jitter, long term jitter, jitter spectrum, SSB phase noise, etc. are terms that have been used to describe various aspects of jitter phenomena. While several jitter measurement techniques have been proposed with associated jitter models and modeling techniques, the relationship among various jitter aspects, and therefore, the relationship among various jitter measurement techniques is not very obvious. This paper analytically clarifies their relationship, and reviews several jitter measurement techniques based on the results of our analytical studies.