Showing papers on "Polysilicon depletion effect published in 2005"

Split-channel antifuse array architecture

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

Back side contact solar cell with doped polysilicon regions

Abstract: In one embodiment, a back side contact solar cell includes a tunnel oxide layer formed on a back side of a substrate. A polysilicon layer is formed on the tunnel oxide layer, and dopant sources are formed on the polysilicon layer. Dopants from the dopant sources are diffused into the polysilicon layer to form p-type and n-type regions therein. The p-type and n-type regions form p-n junctions that, among other advantages, allow for relatively high conversion efficiency.

Substrate backgate for trigate FET

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

N+ poly on high-k dielectric for semiconductor devices

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Dynamic deep depletion field effect transistor

Abstract: A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.

Fully Silicided Metal Gates for High-Performance CMOS Technology: A Review

Abstract: Full silicidation (FUSI) of polysilicon gates promises to be a simple approach for formation of metal gate electrodes for highly scaled complementary metal oxide semiconductor (CMOS) transistors. Devices have been reported with several different silicides, prominently with nickel. NiSi was shown to produce different work functions, covering a large portion of silicon bandgap, in relation to a dopant type and amount present in polysilicon. Elimination of polysilicon gate electrode depletion has been demonstrated. Data indicates that significant reduction of gate tunneling current is possible. A summary of developments of this new approach to metal gates and discussion of issues and challenges of the FUSI process and its applicability to highly scaled technologies is presented.

Transistor array, manufacturing method thereof and image processor

Abstract: An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors.

Polysilicon thin film fabrication method

Abstract: A polysilicon thin film fabrication method is provided, in which a heat-absorbing layer is used to provide sufficient heat for grain growth of an amorphous silicon thin film, and an insulating layer is used to isolate the heat-absorbing layer and the amorphous silicon thin film. A regular heat-conducting layer is used as a cooling source to control the crystallization position and grain size of the amorphous silicon thin film. Therefore, the amorphous silicon thin film can crystallize into a uniform polysilicon thin film, and the electrical characteristics of the polysilicon thin film can be stably controlled.

Method of making a metal gate semiconductor device

Abstract: A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer on the polysilicon gate and to re-expose the previously exposed portion of the metal layer. The re-exposed metal layer is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer. Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate but for the protection provided by the sidewall spacer. After the re-exposed metal has been removed, a transistor is formed in which the metal layer sets the work function of the gate of the transistor.

Method of fabricating a polysilicon layer

Abstract: A method of fabrication a polysilicon layer is provided A substrate is provided and then a buffer layer having a plurality of trenches thereon is formed over the substrate Thereafter, an amorphous silicon layer is formed over the buffer layer Finally, a laser annealing process is conducted so that the amorphous silicon layer melts and crystallizes into a polysilicon layer starting from the upper reach of the trenches This invention can be applied to fabricate the polysilicon layer of a low temperature polysilicon thin film transistor liquid crystal display such that the crystals inside the polysilicon layer are uniformly distributed and have a larger average size

Selective post-doping of gate structures by means of selective oxide growth

Abstract: A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

Contacts for CMOS imagers and method of formation

Abstract: Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.

Maskless multiple sheet polysilicon resistor

Abstract: The invention enables the fabrication of semiconductor devices having polysilicon resistors of different sheet resistance value, without the need to add extra semiconductor fabrication processing steps. An oxide layer is formed over a semiconductor device (104). A polysilicon layer is formed on the oxide layer (106). The polysilicon layer is patterned to form a polysilicon resistor (108). A polysilicon resistor mask having a selected percentage of the polysilicon resistor exposed is formed on the polysilicon resistor (110). A selected dopant is implanted (112), which modifies the resistivity of the polysilicon resistor. The mask is removed (114) and a thermal activation process is performed (116) that diffuses the implanted dopant to a substantially uniform concentration throughout the polysilicon resistor.

Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same

Abstract: A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide formation. A second polysilicon layer is formed over the first polysilicon layer. The first and second polysilicon layers are masked and etched to define transistor structures, some of which comprise the inhibitor and some which are free from the inhibitor. Dielectric spacers are formed, then a metal such as cobalt is deposited over the transistor structures. A thermal process may be used to react the metal with the transistor structures to form fully silicided gates from the inhibitor-free structures and partially silicided gates from the structures comprising the inhibitor. Fully silicided gates have the work function of a metal gate while partially silicided gates may have the work function of doped polysilicon.

Self-aligned photodiode for CMOS image sensor and method of making

Abstract: A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulator may be a combination of silicon oxynitride and silicon dioxide. After formation of the photodiode, the cap insulator layer is removed.

Structure and method of forming a notched gate field effect transistor

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

Polysilicon and silicon dioxide light scatterers for silicon waveguides on five layer substrates

Abstract: A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. FIG. 6 shows a polysilicon and silicon dioxide light scattering element formed on a silicon waveguide. The polysilicon light scatterer is formed on the core of the waveguide with a silicon dioxide layer between the polysilicon and the core. A standard CMOS process is used to form the waveguide and the light scattering element. FIG. 6A is a table summarizing the elements of the light scatterer and the waveguide of FIG. 6 and the CMOS transistors of FIGS. 1 and 2, which are formed from the same materials at the same time on the same substrate. Forming multiple light scatterers on the core of a waveguide can make a grating coupler.

Etching process to avoid polysilicon notching

Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

Method for fabricating field-effect transistor structures with gate electrodes with a metal layer

Abstract: Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is provided and patterned prior to the application of the gate metal. Trenches between the resulting gate structures are filled, and the polysilicon is drawn back to below the top edge of the fillings. The relief formed from the fillings and the polysilicon which has been caused to recede forms a shape which is used to pattern the gate metal without a lithographic step. The provision of a gate sacrificial layer, which is patterned together with the polysilicon layer, makes it possible to form contact structures from a contact metal prior to the application of the gate metal.

On-Chip High-Voltage Charge Pump Circuit in Standard CMOS Processes With Polysilicon Diodes

Abstract: An on-chip high-voltage charge pump circuit realized with the polysilicon diodes in standard (bulk) CMOS process is presented in this paper. Because the polysilicon diodes are fully isolated from the substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the 12-stage charge pump circuit can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (18.9 V) in a 0.25-mum 2.5-V standard CMOS process

Control TFT for OLED display

Abstract: The present invention discloses a control TFT structure (i.e. a driving TFT) for reducing leakage in an OLED display. A semiconductor layer, such as a polysilicon layer, is deposited on a transparent substrate as a channel region. A lightly doped region and a drain region are disposed on one side of the polysilicon layer and a source region is disposed on the opposite side of the polysilicon layer. An insulating layer is deposited covering the surface of the polysilicon layer, the lightly doped region, and the source/drain regions. Source and drain electrodes are disposed in the insulating layer, electrically connecting the source and drain region respectively. A gate metal layer is disposed on the insulating layer, at approximately the top right portion of the polysilicon layer to form a transistor structure.

Method of forming the N-MOS and P-MOS gates of a CMOS semiconductor device

Abstract: A method for forming the N-MOS and P-MOS transistor regions of a CMOS device having reduced depletion of the N and P dopants in the polysilicon gate and reduced penetration of the N and P dopants through the oxide layer and into the channel regions of the N-MOS and the P-MOS transistor. The improvements are accomplished by a new implantation treatment of the polysilicon gate layer prior to implanting the polysilicon layer with the N-type dopant and the P-type dopant for purposes of forming the transistor gates. The implantation treatment prior to the N-type dopant and P-type dopant implantation, includes a first implantation of Ge and/or an inert gas and a second implantation of carbon or fluorine.

Three-dimensional thin-film-transistor silicon-oxide-nitride-oxide-silicon memory cell formed on large grain sized polysilicon films using nuclei induced solid phase crystallization

Abstract: We describe a manufacturing method (US Patent No. 6,713,371) to enhance the grain size of polysilicon films prepared by solid phase crystallization of amorphous silicon films. This technique requires deposition of silicon nuclei between two layers of amorphous silicon films. Grain size is controllable by varying the density of nuclei. Film deposition and crystallization can be conducted with commercially available semiconductor equipments in a single batch. The method does not require extra manufacturing steps after low pressure chemical vapor deposition of silicon films other than solid phase crystallization, making it easy to integrate into a metal-oxide-silicon technology. This article discusses characteristics of polysilicon films and thin-film-transistor-silicon-oxide-nitride-oxide-silicon memory cells formed using the method. Many layers of such cells can be vertically stacked for ultrahigh density file storage applications.

Methods of forming reduced electric field DMOS using self-aligned trench isolation

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping

Abstract: Bulk micromachining technology can be used to produce conducting through-wafer polysilicon interconnects, i.e., polysilicon via plugs. This paper presents the process fabrication steps of polysilicon via plugs with in-situ boron doped polysilicon material in order to develop fast one-step doping process, without additional diffusion. The via holes can be processed by high-aspect ratio silicon etching with inductively coupled plasma (ICP). Only one deep ICP etching is required if the wafer is mechanically ground (from the backside) to reduce the wafer thickness of 500 microns to a typical of 400, in order to overcome deep etching sidewall profile problems. After hole formation with ICP the via plug fabrication process continues by growing an insulating thermal oxide layer with a thickness of the order of a micron, followed by an in-situ boron doped LPCVD polysilicon growth to fill the holes with sufficient step coverage. The polysilicon growth temperature at 680°C ensures sufficient step coverage, reasonable furnace process time and enables planarization processing, such as grinding and chemical-mechanical polishing (CMP). The subsequent planar processing typically requires planarization of the polysilicon layer down to the original silicon (or oxide) surface with CMP, and some doping activation step, which usually can be performed together with some additional oxidation step. Applications of the via plugs in the field of silicon-based sensors or actuators enable significant reduction of the front surface wiring density, which opens additional space for denser packing or other desired components.

Improved analysis of low frequency noise in polycrystalline silicon thin-film transistors

Abstract: An improved analysis of the low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented. The analysis takes into account an exponential energy distribution for the density of states and the flat-band voltage fluctuations for the origin of the drain current noise. Analysis of the drain current spectral density enables the characterization of the gate oxide/polysilicon interface and the active polysilicon layer quality.

Process to integrate fabrication of bipolar devices into a CMOS process flow

Abstract: A BiCMOS method for forming bipolar junction transistors and CMOS devices in a substrate. To avoid erosion of the bipolar junction transistor material layers, gate spacers for the CMOS devices are formed while a bipolar junction transistor photoresist layer is in place. The photoresist layer is used for etching the emitter polysilicon layer (for single polysilicon layer bipolar junction transistors) or for etching the base polysilicon layer (for double polysilicon layer bipolar junction transistors) prior to gate spacer etch.

DNA detection by suspended gate polysilicon thin film transisitor

Abstract: An electronic device, namely suspended gate thin film transistor (SGTFT), for rapid and direct detection of specific DNA sequences with high sensitivity is presented. It is an usual P-type polysilicon TFT where the gate contact is a Si3N4/polysilicon/Si 3N4 bridge suspended at 0.5 mum above the SiO 2/Si3N4 gate insulator. The high field effect due to the low height of the gap induces high sensitivity of the characteristics to any charge variation in the space between the gate and the channel. Amino-substituted ODN is grafted on silicon nitride surface after glutaraldehyde activation. The presence of this grafted ODN is confirmed by the positive shift, meaning the presence of negative charge, of the SGTFT transfer characteristics. The characteristics do not shift with non complementary DNA target. On the contrary, hybridization with complementary DNA is evidenced by the positive shift as large as 0.35 V with 5nM DNA concentration and an effective volume of 7 times 10-10 milliliter