Showing papers on "Silicon on insulator published in 1994"

Ballistic metal-oxide-semiconductor field effect transistor

Abstract: Experiments on ultra‐small metal‐oxide‐semiconductor field effect transistors (MOSFETs) less than 100 nm have been widely reported recently. The frequency of carrier scattering events in these ultra‐small devices is diminished, so that further suppression of carrier scattering may bring these devices close to the regime of ballistic transport. Carrier scattering is suppressed by constructing their channel regions with intrinsic Si and also by low temperature operation. This article proposes the ballistic transport of carriers in MOSFETs, and presents the current‐voltage characteristics of the ballistic n‐channel MOSFET. The current is expressed with the elementary parameters without depending on the carrier mobility. It is independent of the channel length and is proportional to the channel width. The current value saturates as the drain voltage is increased and the triode and the pentode operation are specified as in the conventional MOSFET. Similar current‐voltage characteristics in the ballistic transport regime are also investigated for the p‐channel MOSFET, the dual gate ultra‐thin silicon on insulator MOSFET, and the high electron mobility transistor device. The obtained current gives the maximum current limitation of each field effect transistor geometry. The current control mechanism of ballistic MOSFETs is discussed. The current value is governed by the product of the carrier density near the source edge in the channel, and the velocity with which carriers are injected from the source into the channel.Influence of optical phonon emission to the transport is discussed. It is suggested that if the device is operated with relatively low carrier density at low temperatures, and if the scattering processes other than the optical phonon emission are suppressed so as to attain the ballistic transport, the optical phonon emission is also suppressed and ballistic transport is sustained. A convenient figure of merit to show the ballisticity of carrier transport in an experimental MOSFET is proposed. Its value is estimated for some examples of the recent ultra‐small MOSFET experiment. The proposed current voltage characteristics are evaluated for a dual gate silicon on insulator MOSFET geometry. The result is compared with the recently reported elaborate Monte Carlo simulation with satisfactory agreement.

Measurement and modeling of self-heating in SOI nMOSFET's

Abstract: Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >

Epitaxial layer transfer by bond and etch back of porous Si

Abstract: We demonstrate a novel method for bond and etch back silicon on insulator in which an epitaxial Si layer over porous Si is transferred onto a dissimilar substrate by bonding and etch back of porous Si. The highest etching selectivity (100 000:1) between the porous Si and the epitaxial layer is achieved by the alkali free solution of HF, H2O2, and H2O which is essential for this single etch‐stop method to produce a submicron‐thick active layer with superior thickness uniformity (473±14 nm) across a 5 in. silicon‐on‐insulator wafer.

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

Silicon-on-insulator optical rib waveguide loss and mode characteristics

Abstract: Optical rib waveguides with rib heights of 3.17 and 7.67 microns with various widths have been formed in separation by implantation of oxygen (SIMOX) based silicon-on-insulator (SOI) structures. The effect of waveguide rib etch depth, width, and interface roughness on loss and mode characteristics have been studied at wavelengths of 1.15 and 1.523 microns. The experimental results support the hypothesis that certain rib dimensions can lead to single mode SOI waveguides even though planar SOI waveguides of similar multimicron dimension are not single mode. Mode loss was found to be strongly dependent on interface roughness and mode confinement. >

New approach to the growth of low dislocation relaxed SiGe material

Abstract: In this growth process a new strain relief mechanism operates, whereby the SiGe epitaxial layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an ultrathin silicon on insulator (SOI) substrate with a superficial silicon thickness less than the SiGe layer thickness. Initially, the thin Si layer is put under tension due to an equalization of the strain between the Si and SiGe layers. Thereafter, the strain created in the thin Si layer relaxes by plastic deformation. Since the dislocations are formed and glide in the thin Si layer, no threading dislocation is ever introduced in to the upper SiGe material, which appeared dislocation free to the limit of the cross sectional transmission electron microscopy analysis. We thus have a method for producing very low dislocation, relaxes SiGe films with the additional benefit of an SOI substrate.

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

Abstract: A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V. >

Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers

Abstract: A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.

Three-terminal gate-controlled semiconductor switching device with rectifying-gate

Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET). To turn-on the device, the gate electrode is biased positive and an inversion layer channel of relatively low resistance is formed in the silicon active region. The channel electrically connects the source of the silicon carbide MESFET (or JFET) with the source of the silicon MOSFET to thereby turn-on the device when a positive drain bias is applied.

A capacitorless dram device on silicon-on-insulator substrate

Abstract: A DRAM device has a first semiconductor region (18) of one conductivity on the silicon film of a silicon-on-insulator substrate (22). A second (16) and a third (14) semiconductor region of the opposite conductivity are formed in the first semiconductor region (18). A fourth semiconductor region (12) of the same conductivity type as the first semiconductor region (18) is formed within the second semiconductor region (16) with higher doping concentration. A insulating layer (11) is formed on the semiconductor surface. On top of the insulating layer (11), a gate electrode (10) is formed and is at least partially overlapped with the first (18), the second (16), the third (14), and the fourth (12) semiconductor region. A storage node (24) is formed in the first semiconductor region (18) between the second (16) and the third (14) semiconductor region where the information is stored. The amount of charge stored in the storage node (24) is controlled by a first transistor including the fourth semiconductor region (12), the second semiconductor region (16), the storage node (24), and the gate electrode (10).

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Abstract: For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

SOI trench DRAM cell for 256 MB DRAM and beyond

Abstract: A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the conventional substrate plate trench cell. The SOI cell eliminates the parasitic trench sidewall leakage, reduces soft errors, eliminates well to substrate leakage, in addition to all the other advantages of SOI devices.

Soi substrate fabrication

Abstract: A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.

Hydrogen annealed silicon-on-insulator

Abstract: Hydrogen annealing effects on silicon‐on‐insulator (SOI) materials are reported. High boron concentration of ∼2×1018/cm3 in 0.1‐μm‐thick SOI layer produced by bond and etch‐back SOI (BESOI) method is reduced to ∼ 5×1015/cm3 by annealing at 1150 °C for 1 h. The BESOI surface became very smooth comparable to commercially available polished wafer simultaneously. Separation‐by‐implantation‐of‐oxygen wafer was also smoothed by the hydrogen anneal. This is due to surface migration of Si atoms driven by surface energy minimization after removing native oxide.

Silicon-on-insulator optical rib waveguides: loss, mode characteristics, bends and y-junctions

Abstract: Optical rib waveguides with widths from 2.73 to 7.73 microns have been formed in SIMOX-based silicon-on-insulator (SOI) structures consisting of a 4.32 micron thick surface-silicon layer and a 0.398 micron buried-oxide layer. The effect of waveguide width, bend radius, y-junction splitting and interface roughness on loss and mode characteristics have been studied at wavelengths of 1.15 and 1.523 microns. The experimental results support the hypothesis that certain rib dimensions can lead to single-mode waveguides even though planar SOI waveguides of similar multimicron dimension are multimode. The propagation losses of waveguides 3.72 microns wide were found to be nominally 0.0 dB/cm and 0.4 dB/cm for the TE and TM modes, respectively, when measured at 1.523 microns, where the measurement error was +or-0.5 dB/cm. This means that the loss is experimentally indistinguishable from pure bulk silicon. These results are thought to be the lowest loss measurements for silicon integrated optical waveguides reported to date.

Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Abstract: Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 /spl mu/m regime may favor partially depleted devices. >

Silicon‐on‐lnsulator Devices for High Voltage and Power IC Applications

Abstract: Silicon-on-insulator (SOI) technology based on wafer bonding promises to deliver significant performance advantages and cost reduction over the existing bulk silicon technologies used for making power integrated circuits. A review is presented of the fundamental considerations that arise in the study of SOI devices for high-voltage applications. Significant device design parameters, such as the off-state breakdown voltage, on-state specific resistance, thermal dissipation, packing density, and manufacturability are discussed in the context of the applicable device physics and SOI material requirements. Several possible approaches for achieving high breakdown voltages in SOI devices are described. The advantages and limitations of each approach are discussed and illustrated with some recent results on experimental devices.

140-GHz metal-semiconductor-metal photodetectors on silicon-on-insulator substrate with a scaled active layer

Abstract: Metal‐semiconductor‐metal photodetectors with 100‐nm finger spacing and width on a silicon‐on‐insulator substrate that has a scaled active layer were fabricated and characterized using electro‐optic sampling. The unique device structure cuts off carriers generated deep inside the semiconductor substrate, resulting in a measured response time of 3.2 ps and a bandwidth of 140 GHz. Furthermore, the detector structure makes the detector’s speed independent of the light penetration depth and thus the light wavelength. Good metal‐semiconductor Schottky contact and low detector dark current have been achieved.

Fabrication of defect free silicon on an insulating substrate

Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.

SOI (Silicon-on-insulator) for high speed ultra large scale integration

Abstract: Bulk complementary metal-oxide-semiconductor (CMOS) technology scaling can not sustain the historical rate of speed increase. A realistic target for silicon-on-insulator (SOI) delay and power reductions in comparison to bulk technology are 40% and 30%, independent of scaling, mostly through capacitance reduction. Denser isolation allows more compact layout and easy integration of different high speed (E/D NMOS), low power (CMOS), analog (bipolar, grounded-body CMOS) and memory devices. Silicon device speed record (13 ps at 1.5 V, 300 K) has been set with SOI E/D NMOS. Leakage current due to steady state and transient floating-body induced threshold lowering (FITL) is a device issue which deserves more attention.

Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness

Abstract: A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness T BOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage V SS of a low-voltage power supply and the voltage V DD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following equation: T.sub.BOX >(V.sub.DD -V.sub.SS -K.sub.2)/K.sub.1 where K 1 .tbd.e BOX (Q BN +Q BP ), K 2 .tbd.2Φ FN +2Φ FP -1.03, e BOX -1 is the dielectric constant of the base insulation layer, Q BN and Q BP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and Φ FN and Φ FP are pseudo Fermi potentials of the NMOS and PMOS transistors.

Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI

Abstract: A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the device capacitances are reduced, and the transistor can be combined with fully-depleted CMOS in a SOI-BiCMOS technology.

Method for producing a silicon-on-insulator capacitive surface micromachined absolute pressure sensor

Abstract: A method and structure for forming a capacitive transducer having a deformable single crystal diaphragm. A first well region is formed within a semiconductor substrate in an SOI wafer having a sacrificial layer of known thickness and a top single-crystal silicon layer thereon. Next, a silicon, epitaxial layer is deposited on the top silicon layer for forming a flexible single crystal membrane. The epitaxial layer and the sacrificial layer are masked and etched to define the flexible diaphragm. An electrical insulating conformal support layer is deposited on the substrate and attached to the diaphragm so as to seal the sacrificial layer therebetween. An access opening is etched through the diaphragm, and then a wet etchant is inserted through the access opening for removing the sacrificial layer, thereby defining a diaphragm cavity between the remaining epitaxial layer and the substrate. Conductive ions are diffused into facing sections of the diaphragm and the first well of the substrate so as to define fixed and deformable electrodes of the sensing capacitor. Next, a plug is selectively deposited within and for sealing the access opening without substantially reducing the volume of the diaphragm cavity.

Lateral Semiconductor-on-Insulator (SOI) semiconductor device having a lateral drift region

Abstract: A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor on the insulating layer. The semiconductor device includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region on the buried insulating layer, and a drain region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. According to the invention a portion of the semiconductor device is made in a first semiconductor material and the lateral drift region comprises a wide bandgap second semiconductor material. The first semiconductor material, such as silicon or germanium or a combination of both, is easy to process, whereas the wide bandgap second material gives high breakdown voltage and good operational characteristics.

Reach-through isolation silicon-on-insulator device

Abstract: A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate

Abstract: A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO 2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g. Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO 2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit. Generally, relatively thinner regions can be used for faster speed devices and relatively thicker regions can be used for greater current carrying capability. The novel technique of depositing, patterning and etching a layer of screening material before implantation can also be used to create a substrate with both bulk and SOI substrate regions, with different portions of a circuit built in each region. Generally, such a substrate can be used to create integrated circuits that have high voltage isolation between different blocks of the circuit. The SOI/bulk substrate can also be used to fabricate integrated circuits which contain low voltage logic and which also regulate large amounts of current at high voltage.

Analytical surface potential expression for thin-film double-gate SOI MOSFETs

Abstract: Using a perturbation theory, we derived an analytical surface potential expression for subthreshold and strong-inversion regions. This enabled us to derive analytical models for the subthreshold slope, threshold voltage, and induced electron concentration of a double-gate SOI MOSFET. We also clarified the dependence of the device characteristics on device parameters, and explained the ideal subthreshold factor. We do not expect volume inversion in practical devices. Our models' predictions agree well with numerical and experimental data.

A novel Silicon-On-Insulator (SOI) MOSFET for ultra low voltage operation

Abstract: To extend the lower bound of power supply voltage, we propose a variable threshold voltage MOSFET (VTMOS) built on silicon-on-insulator (SOI). Threshold voltage of VTMOS drops as gate voltage is raised, resulting in a much higher current drive than regular MOSEET, at low Vdd. On the other hand, V/sub t/ is high at V/sub gs/=O, thus the leakage current is low. The SOI devices used in the study were built on SIMOX wafers. A four terminal layout was used to provide separate source, drain, gate, and body contacts.

SOI (silicon on insulator) substrate with enhanced gettering effects

Abstract: A silicon-on-insulator (SOI) substrate is arranged such that a polycrystalline silicon film which functions as a gettering site for heavy metals is provided on a first single crystal silicon substrate, a silicon oxide island film is partially provided in a polycrystalline silicon film, and a second single crystal silicon substrate is provided on an entire upper surface of the polycrystalline silicon film. An element isolation trench extends from an upper surface of the second single crystal silicon substrate to an upper surface of the first single crystal silicon substrate, and a silicon oxide film is buried in the element isolation trench. The SOI substrate thus constituted has a high gettering effect for heavy metals.

The kink-related excess low-frequency noise in silicon-on-insulator MOST's

Abstract: The phenomenology of the kink-related low-frequency (LF) noise overshoot in partially depleted (PD) silicon-on-insulator (SOI) MOS transistors is described in detail. The influence of various physical parameters is reported. Based on the observations, a comprehensive first-order theory for the feature is derived. The model is based on the charge fluctuations which are caused by deep-level assisted generation-recombination events in the depletion region of the transistor. It will be shown that the noise amplitude is proportional to the density of deep-level centers, while the peak position is a sensitive function of the saturation voltage. This follows from the postulated dependence of the capture time on the inverse substrate current. As will be shown, the standard expression for the multiplication current is in first order also valid for SOI MOST's, both at room temperature and at 77 K. Simulations demonstrate that the proposed model correctly predicts the dependence of the noise overshoot on the measurement frequency, on the gate voltage, the temperature and on the device length. Finally, the spectroscopic potential of the feature will be outlined and possible ways to render the technique truly quantitative are pointed out. >