Showing papers on "Simulated annealing published in 1988"

Cooling Schedules for Optimal Annealing

Abstract: A Monte Carlo optimization technique called “simulated annealing” is a descent algorithm modified by random ascent moves in order to escape local minima which are not global minima. The level of randomization is determined by a control parameter T, called temperature, which tends to zero according to a deterministic “cooling schedule.” We give a simple necessary and sufficient condition on the cooling schedule for the algorithm state to converge in probability to the set of globally minimum cost states. In the special case that the cooling schedule has parametric form Tt = c/log1 + t, the condition for convergence is that c be greater than or equal to the depth, suitably defined, of the deepest local minimum which is not a global minimum state.

Global optimization and simulated annealing

Abstract: In this paper we are concerned with global optimization, which can be defined as the problem of finding points on a bounded subset of Rn in which some real valued functionf assumes its optimal (i.e. maximal or minimal) value. We present a stochastic approach which is based on the simulated annealing algorithm. The approach closely follows the formulation of the simulated annealing algorithm as originally given for discrete optimization problems. The mathematic formulation is extended to continuous optimization problems and we prove asymptotic convergence to the set of global optima. Furthermore, we discuss an implementation of the algorithm and compare its performance with other well known algorithms. The performance evaluation is carried out for a standard set of test functions from the literature. Keywords: global optimization, continuous variables, simulated annealing.

On automatic feature selection

Abstract: We review recent research on methods for selecting features for multidimensional pattern classification. These methods include nonmonotonicity-tolerant branch-and-bound search and beam search. We describe the potential benefits of Monte Carlo approaches such as simulated annealing and genetic algorithms. We compare these methods to facilitate the planning of future research on feature selection.

Optimization of large join queries

Abstract: We investigate the problem of optimizing Select—Project—Join queries with large numbers of joins. Taking advantage of commonly used heuristics, the problem is reduced to that of determining the optimal join order. This is a hard combinatorial optimization problem. Some general techniques, such as iterative improvement and simulated annealing, have often proved effective in attacking a wide variety of combinatorial optimization problems. In this paper, we apply these general algorithms to the large join query optimization problem. We use the statistical techniques of factorial experiments and analysis of variance (ANOVA) to obtain reliable values for the parameters of these algorithms and to compare these algorithms. One interesting result of our experiments is that the relatively simple iterative improvement proves to be better than all the other algorithms (included the more complex simulated annealing). We also find that the general algorithms do quite well at the maximum time limit.

Simulated Annealing for VLSI Design

Abstract: 1. Introduction.- 1.1. Combinatorial Optimization.- 1.2. The Method of Simulated Annealing.- 1.3. Remarks.- 2. Placement.- 2.1. Introduction.- 2.2. Gate-Array Placement.- 2.2.1. The K-G-V Algorithm.- 2.2.2. TimberWolf.- 2.3. Standard-Cell Placement.- 2.3.1. TimberWolf.- 2.3.2. Another Approach.- 2.4. Macro/Custom-Cell Placement.- 2.4.1. Jespen and Gelatt's Algorithm.- 2.4.2. TimberWolf.- 2.5. Other Stochastic Algorithms.- 2.5.1. Genetic Placement.- 2.5.2. Simulated Evolution Placement.- 2.6. Concluding Remarks.- 3. Floorplan Design.- 3.1. Introduction.- 3.2. Part 1: Rectangular Modules.- 3.2.1. Slicing Floorplans.- 3.2.2. Solution Space.- 3.2.3. Neighboring Solutions.- 3.2.4. Cost Function.- 3.2.5. Annealing Schedule.- 3.2.6. Experimental Results.- 3.3. Part 2: Rectangular and L-Shaped Modules.- 3.3.1. Geometric Figures.- 3.3.2. The Operators.- 3.3.3. Floorplan Representation.- 3.3.4. The Algorithm.- 3.3.5. Experimental Results.- 3.4. Concluding Remarks.- 4. Channel Routing.- 4.1. Introduction.- 4.2. The Channel Routing Problem.- 4.3. The Channel Router SACR.- 4.3.1. Solution Space.- 4.3.2. Neighboring Solutions.- 4.3.3. Cost Function.- 4.3.4. Annealing Schedule.- 4.3.5. Fast Approximation Scheme.- 4.4. The Channel Router SACR2.- 4.5. Experimental Results and Discussion.- 4.6. Concluding Remarks.- 5. Permutation Channel Routing.- 5.1. Introduction.- 5.2. Motivation and Applications.- 5.3. NP-Completeness Results.- 5.4. First Method - Simulated Annealing.- 5.4.1. Neighboring Solutions.- 5.4.2. Cost Function.- 5.4.3. Annealing Schedule.- 5.5. Second Method - Iterative Improvement.- 5.5.1. The Iterative Improvement Scheme.- 5.5.2. Version-D.- 5.5.3. Version-C.- 5.5.4. Choice of Initial Solution.- 5.6. Experimental Results.- 5.7. Concluding Remarks.- 6. PLA Folding.- 6.1. Introduction.- 6.2. The PLA Folding Problem.- 6.3. The PLA Folding Algorithm.- 6.3.1. Solution Space.- 6.3.2. Neighboring Solutions.- 6.3.3. Cost Function.- 6.3.4. Annealing Schedule.- 6.4. Multiple-Folded PLA Realization.- 6.5. Constrained Multiple Folding.- 6.6. Simple Folding.- 6.7. Experimental Results and Discussions.- 6.8. Concluding Remarks.- 7. Gate Matrix Layout.- 7.1. Introduction.- 7.2. Problem Formulation.- 7.3. Generalized Problem Formulation.- 7.4. Advantages of the Generalized Formulation.- 7.5. The Simulated Annealing Method.- 7.5.1. Solution Space.- 7.5.2. Neighboring Solutions.- 7.5.3. Cost Function.- 7.5.4. Annealing Schedule.- 7.6. Experimental Results.- 7.7. Concluding Remarks.- 8. Array Optimization.- 8.1. Introduction.- 8.2. The Array Optimization Problem.- 8.3. Definitions.- 8.4. The Array Optimization Algorithm.- 8.4.1. The Algorithm Column-Fold.- 8.4.2. The Algorithm Row-Fold.- 8.4.3. The Solution Space.- 8.4.4. The Main Folding Algorithm.- 8.5. Experimental Results.- 8.6. Concluding Remarks.- References.

Simulated annealing - an annotated bibliography

Abstract: SYNOPTIC ABSTRACTThe results of an extensive literature survey of the Simulated Annealing algorithm for optimization problems are reported. The papers and books are classified and annotated, with particular reference to the type of cooling schedule employed.

VLSI Placement and Global Routing Using Simulated Annealing

Abstract: 1 Introduction.- 1.1 Placement and Global Routing of Integrated Circuits.- 1.2.1 The gate array placement and global routing problem.- 1.2.2 The standard cell placement and global routing problem.- 1.2.3 The macro/custom cell placement and global routing problem.- 1.3 Previous Approaches to Placement and Global Routing.- 1.3.1 Previous placement methods.- 1.3.2 Previous global routing methods.- 1.4 A New Approach to Cell-Based Placement and Global Routing.- 2 The Simulated Annealing Algorithm.- 2.1 Introduction.- 2.2 The Basic Simulated Annealing Algorithm.- 2.3 Theoretical Investigations of the Simulated Annealing Algorithm.- 2.4 Overview of Work on General Annealing Schedules.- 2.4.1 The initial temperature.- 2.4.2 The temperature decrement.- 2.4.3 The equilibrium condition.- 2.4.4 The stopping, or convergence, criterion.- 2.5 Implementations of Simulated Annealing for Placement and Global Routing.- 2.6 The Function f().- 2.7 Fast Evaluation of the Exponential Function.- 3 Placement and Global Routing of Standard Cell Integrated Circuits.- 3.1 Introduction.- 3.2 The General TimberWolfSC Methodology.- 3.2.1 Finding the optimal target row lengths.- 3.2.2 Critical-net weighting.- 3.3 The Algorithm for Stage 1 of TimberWolfSC.- 3.3.1 The cost function.- 3.3.1.1 The first term in the cost function.- 3.3.1.2 The second term in the cost function.- 3.3.1.3 The third term in the cost function.- 3.3.2 An alternative objective function.- 3.3.3 The generation of new states function.- 3.3.4 The inner loop criterion.- 3.3.5 The range limiter.- 3.3.6 The control of T.- 3.3.7 The effects of net weighting.- 3.4 The Algorithms for Stage 2 of TimberWolfSC.- 3.4.1 Implementation of the stage 2 simulated annealing functions.- 3.4.2 The first phase of the global router.- 3.4.3 The second phase of the global router.- 3.5 The Algorithm for Stage 3 of TimberWolfSC.- 3.6 TimberWolfSC Results.- 3.6.1 Comparisons taken at the end of stage 1.- 3.6.2 The effectiveness of the global router.- 3.6.3 The effectiveness of stage 3 of TimberWolfSC.- 3.6.4 TimberWolfSC comparisons including stage 3.- 4 Macro/Custom Cell Chip-Planning, Placement, and Global Routing.- 4.1 Introduction.- 4.2 The General TimberWolfMC Methodology.- 4.2.1 Algorithms for handling rectilinear ceils.- 4.2.1.1 The bust() algorithm.- 4.2.1.2 The unbust() algorithm.- 4.2.2 Generating the initial placement configuration.- 4.2.3 Custom-cell pin placement.- 4.2.3.1 Introduction to the TimberWolfMC pin site methodology.- 4.3 The Algorithm for Stage 1 of TimberWolfMC.- 4.3.1 The cost function.- 4.3.1.1 The first term in the cost function.- 4.3.1.2 The second term in the cost function.- 4.3.1.3 The third term in the cost function.- 4.3.2 The generate() function.- 4.3.2.1 Introduction.- 4.3.2.2 The Range Limiter.- 4.3.2.3 Single-cell displacement-point selection.- 4.3.3 Additional stage 1 simulated annealing algorithmic details.- 4.4 The Algorithms for Stage 2 of TimberWolfMC.- 4.4.1 Channel generation.- 4.4.2 Global routing.- 4.4.3 Placement refinement.- 4.5 TimberWolfMC Results.- 4.6 Conclusion.- 5 Average Interconnection Length Estimation.- 5.1 Introduction.- 5.2 The Placement Model.- 5.3 Previous Approaches.- 5.4 Average Interconnection Length for Random Placements under the Assumption of Two-Pin Nets.- 5.4.1 Practical considerations.- 5.5 Average Interconnection Length for Random Placements Having Nets of Arbitrary Pin Counts.- 5.5.1 Results.- 5.6 A Model for Optimized Placement.- 5.6.1 The average number of other cells connected to a cell.- 5.6.1.1 The new method.- 5.6.1.2 Practical considerations.- 5.6.1.3 Results.- 5.6.2 A notion of optimized placement.- 5.6.3 The enclosing Cm x Cs rectangles.- 5.7 Results.- 6 Interconnect-Area Estimation for Macro Cell Placements.- 6.1 Introduction.- 6.2 Interconnect-Area Estimation Based on Average Net Traffic.- 6.3 Baseline Channel Width Modulation Based on Channel Position.- 6.4 Associating the Estimated Interconnect Area with the Cell Edges.- 6.5 Interconnect-Area Estimation as a Function of Relative Pin Density.- 6.6 The Implementation of the Dynamic Interconnect-Area Estimator.- 6.7 Results.- 7 An Edge-Based Channel Definition Algorithm for Rectilinear Cells.- 7.1 Introduction.- 7.2 The Basic Channel Definition Algorithm.- 7.2.1 Identifying critical cell-edge pairs.- 7.2.2 Characterization of fixed cell edges.- 7.2.3 An algorithm for finding critical regions.- 7.3 The Generation of the Channel Graph.- 7.4 The Generation of the Channel Routing Order.- 8 A Graph-Based Global Router Algorithm.- 8.1 Introduction.- 8.2 Basic Graph Algorithms Used by the Global Router.- 8.2.1 Prim's algorithm for the minimum spanning tree problem.- 8.2.2 Dijkstra's algorithm for the shortest path problem.- 8.2.3 Lawler's algorithm for finding the M-shortest paths.- 8.3 The Algorithm for Generating M-Shortest Routes for a Net.- 8.4 The Second Phase of the Global Router Algorithm.- 8.5 Results.- 9 Conclusion.- 9.1 Summary.- 9.2 Future Work.- 9.2.1 Simulated annealing.- 9.2.2 Row-based cell placement.- 9.2.3 Row-based global routing.- 9.2.4 Macro/custom cell placement.- 9.2.5 Interconnection length estimation.- 9.2.6 Channel definition.- 9.2.7 Graph-based global routing.- Appendix Island-Style Gate Array Placement.- A.1 Introduction.- A.2 The Implementation of the Simulated Annealing Functions.- A.2.1 The generation of new states.- A.2.2 The cost function.- A.2.2.1 The first cost function.- A.2.2.2 The second cost function.- A.2.3 The inner loop criterion.- A.2.5 The stopping criterion.- A.3 Results.- A.3.1 Performance comparison of the two cost functions.- A.3.2 Performance comparison on benchmark problems.

Simulated annealing via Sobolev inequalities

Abstract: We use Sobolev inequalities to study the simulated annealing algorithm. This approach takes advantage of the local time reversibility of the process and yields the optimal “freezing schedule” as well as quantitative information about the rate at which the process is tending to its ground state.

A simulated annealing approach to the multiconstraint zero-one knapsack problem

Abstract: The multiconstraint 0–1 knapsack problem encounters when deciding how to use a knapsack with multiple resource constraints. The problem is known to be NP-hard, thus a “good” algorithm for its optimal solution is very unlikely to exist. We show how the concept of simulated annealing may be used for solving this problem approximately. 57 data sets from literature demonstrate, that the algorithm converges very rapidly towards the optimum solution.

The time complexity of maximum matching by simulated annealing

Abstract: The random, heuristic search algorithm called simulated annealing is considered for the problem of finding the maximum cardinality matching in a graph. It is shown that neither a basic form of the algorithm, nor any other algorithm in a fairly large related class of algorithms, can find maximum cardinality matchings such that the average time required grows as a polynomial in the number of nodes of the graph. In contrast, it is also shown for arbitrary graphs that a degenerate form of the basic annealing algorithm (obtained by letting “temperature” be a suitably chosen constant) produces matchings with nearly maximum cardinality in polynomial average time.

Performance of a new annealing schedule

Abstract: A new simulated annealing schedule has been developed; its application to the standard cell placement and the traveling salesman problems results in a two to twenty-four times speedup over annealing schedules currently available in the literature. Since it uses only statistical quantities, the annealing schedule is applicable to general combinatorial optimization problems.

Optimization by Mean Field Annealing

Abstract: Nearly optimal solutions to many combinatorial problems can be found using stochastic simulated annealing. This paper extends the concept of simulated annealing from its original formulation as a Markov process to a new formulation based on mean field theory. Mean field annealing essentially replaces the discrete degrees of freedom in simulated annealing with their average values as computed by the mean field approximation. The net result is that equilibrium at a given temperature is achieved 1-2 orders of magnitude faster than with simulated annealing. A general framework for the mean field annealing algorithm is derived, and its relationship to Hopfield networks is shown. The behavior of MFA is examined both analytically and experimentally for a generic combinatorial optimization problem: graph bipartitioning. This analysis indicates the presence of critical temperatures which could be important in improving the performance of neural networks.

A Quantitative Analysis of the Simulated Annealing Algorithm: A Case Study for the Traveling Salesman Problem

Abstract: A quantitative study is presented of the typical behavior of the simulated annealing algorithm based on a cooling schedule presented previously by the authors. The study is based on the analysis of numerical results obtained by systematically applying the algorithm to a 100-city traveling salesman problem. The expectation and the variance of the cost are analyzed as a function of the control parameter of the cooling schedule. A semiempirical average-case performance analysis is presented from which estimates are obtained on the expectation of the average final result obtained by the simulated annealing algorithm as a function of the distance parameter, which determines the decrement of the control parameter.

Maximum likelihood parameter estimation by simulated annealing

Abstract: The author presents a method for finding the maximum-likelihood estimates of a set of signal parameters. The algorithm is based on simulated annealing, which is a form of stochastic optimization that has been found to be a powerful technique for solving multidimensional combinatorial optimization problems. He also presents a simulated annealing solution to a typical parameter estimation problem that arises in sensor array processing, and some experimental results are included which demonstrate the power of annealing compared to existing algorithms. It is pointed out that simulated annealing is quite a general optimization procedure and should find a wide range of applications. >

Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

Abstract: The algorithms and the implementation of a new macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the interconnect area around the individual cells is determined using a new dynamic interconnect area estimator. The second stage consists of: (1) a channel definition step, using a new channel definition algorithm, (2) a global routing step, using a new global router algorithm, and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interconnect length savings of 8 to 49 percent were achieved in experiments on 9 industrial circuits. Furthermore, circuit-area reductions ranged from 4 to 56 percent versus a variety of other placement methods.

A novel principle for optimization of the instantaneous Fourier plane coverage of correction arrays

Abstract: A novel principle for the design of correlation arrays is introduced, based upon the maximization of the distance between samples. Simulated annealing is applied to the problem of finding solutions for moderate numbers of elements (up to 12). The resulting arrays have symmetric crystalline structures. >

A traveling salesman objective function that works

Abstract: An Ising-like objective function has been used by J. Hopfield (1985) and others for finding the optimal tour in a traveling salesman problem using a neural network. This function contains four terms: one which reflects the length of the tour and three more penalty terms which attempt to maintain a feasible solution. These terms are combined into a weighted sum using four coefficients determined by the user. The quality of the final solution is very sensitive to these weighting factors, and good values for them are difficult to find when even a moderate number of cities are considered. A novel objective function is developed here that requires one weighting factor the value of which is easily determined. The use of this function in combination with an algorithm combining characteristics of neural networks and simulated annealing allows good, valid solutions to be found. >

Parallel standard cell placement algorithms with quality equivalent to simulated annealing

Abstract: An algorithm called heuristic spanning creates parallelism by simultaneously investigating different areas of the plausible combinatorial search space. It is used to replace the high-temperature portion of simulated annealing. The low-temperature portion of simulated annealing is sped up by a technique called section annealing, in which placement is geographically divided and the pieces are assigned to separate processors. Each processor generates simulated-annealing-style moves for the cells in its area and communicates the moves to other processors as necessary. Heuristic spanning and section annealing are shown experimentally to converge to the same final cost function as regular simulated annealing. These approaches achieve significant speedup over uniprocessor simulated annealing, giving high-quality VLSI placement of standard cells in a short period of time. >

Simulated annealing and codebook design

Abstract: The application of simulated annealing to the design of a codebook for a vector quantizer (VQ) that is used to code images are studied. The traditional method for VQ codebook design is to use the generalized Lloyd algorithm (GLA), an iterative optimization procedure where an initial codebook is continually refined so that each iteration reduces the distortion involved in coding a given training set. However, this algorithm easily gets trapped in local minima of the distortion, resulting in a suboptimal codebook. Simulated annealing is a procedure that uses randomness in a search algorithm and tends to skirt relatively poor local minima in favor of better ones. The mean-squared-error (MSE) is used as the distortion measure during the design, and coded images are evaluated both subjectively and in terms of the peak-signal-to-noise ratio. >

Optimization by neural networks

Abstract: The ability to map and solve a number of interesting problems on neural networks motivates a proposal for using neural networks as a highly parallel model for general-purpose computing. The author review this proposal, showing how to map combinational optimization problems, including graph K-partitioning, vertex cover, maximum independent set, maximum clique, number partitioning, and maximum matching. They report that performance results are quite encouraging; the solutions for graph partitioning and task allocation problems are comparable to those obtained using heuristics and the running times are significantly lower than those required using simulated annealing. >

Task allocation onto a hypercube by recursive mincut bipartitioning

Abstract: An efficient recursive task allocation scheme, based on the Kernighan-Lin mincut bisection heuristic, is proposed for the effective mapping of tasks of a parallel program onto a hypercube parallel computer. It is evaluated by comparison with an adaptive, scaled simulated annealing method. The recursive allocation scheme is shown to be effective on a number of large test task graphs - its solution quality is nearly as good as that produced by simulated annealing, and its computation time is several orders of magnitude less.

Processor and Link Assignment in Multicomputers Using Simulated Annealing.

Abstract: In the design of multicomputer systems, the scheduling and mapping of a parallel algorithm onto a host architecture has a critical impact on overall system performance. In this paper we develop a graph-based solution to both aspects of the mapping problem using the simulated annealing optimization heuristic. A two phase mapping strategy is formulated: I) process annealing assigns parallel processes to processing nodes, and 2) connection annealing schedules traffic connections on network data links so that interprocess conllnunication conflicts are minimized. To evaluate the quality of generated mappings, cost functions suitable for simulated annealing are derived that accurately quantify communication overhead. Application examples are presented using the hypercube as a host architecture, with host graphs containing up to 512 nodes.

Performance of a simulated-annealing algorithm for phase retrieval

Abstract: We report computer observations on the performance of an improved version of a simulated-annealing algorithm that was used before for the problem of phase retrieval. According to the results, we propose to use this method in conjunction with the algorithm of Fienup [ Opt. Lett.3, 27 ( 1978);Opt. Eng.18529, ( 1979);Appl. Opt.21, 2758 ( 1982). The full power of the simulated-annealing algorithm with large arrays appears to be limited by present-day computers rather than by its numerical performance, but we believe that this combination may constitute an efficient method for phase retrieval.

Stochastic neural networks for solving job-shop scheduling. I. Problem representation

Abstract: An application of neural networks is presented for solving job-shop scheduling, and NP-complete optimization problem with constraint satisfaction. In particular, the authors introduce a neural computation architecture based on a stochastic Hopfield neural-network model. First, the job-shop problem is mapped into a two-dimensional matrix representation of neurons similar to those for solving the traveling salesman problem (TSP). Constant positive and negative current biases are applied to specific neurons as excitations and inhibitions, respectively, to enforce the operation precedence relationships. At the convergence of the neural network, solution to the job-shop problem is represented by a set of cost function trees encoded in the matrix of stable states. Each node represents a job, and each link represents the interdependency between jobs. The cost attached to each link is a function of the processing time of a particular job. The starting time of each job can be determined by traversing the paths leading to the root node of the tree. Near-optimal and optimal solutions are found by simulated annealing. >