Showing papers on "Switched capacitor published in 2008"

Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters

Abstract: A few simple switching structures, formed by either two capacitors and two-three diodes (C-switching), or two inductors and two-three diodes (L-switching) are proposed. These structures can be of two types: ldquostep-downrdquo and ldquostep-up.rdquo These blocks are inserted in classical converters: buck, boost, buck-boost, Cuk, Zeta, Sepic. The ldquostep-downrdquo C- or L-switching structures can be combined with the buck, buck-boost, Cuk, Zeta, Sepic converters in order to get a step-down function. When the active switch of the converter is on, the inductors in the L-switching blocks are charged in series or the capacitors in the C-switching blocks are discharged in parallel. When the active switch is off, the inductors in the L-switching blocks are discharged in parallel or the capacitors in the C-switching blocks are charged in series. The ldquostep-uprdquo C- or L-switching structures are combined with the boost, buck-boost, Cuk, Zeta, Sepic converters, to get a step-up function. The steady-state analysis of the new hybrid converters allows for determing their DC line-to-output voltage ratio. The gain formula shows that the hybrid converters are able to reduce/increase the line voltage more times than the original, classical converters. The proposed hybrid converters contain the same number of elements as the quadratic converters. Their performances (DC gain, voltage and current stresses on the active switch and diodes, currents through the inductors) are compared to those of the available quadratic converters. The superiority of the new, hybrid converters is mainly based on less energy in the magnetic field, leading to saving in the size and cost of the inductors, and less current stresses in the switching elements, leading to smaller conduction losses. Experimental results confirm the theoretical analysis.

Analysis and Optimization of Switched-Capacitor DC–DC Converters

Abstract: Analysis methods are developed that fully determine a switched-capacitor (SC) dc-dc converter's steady-state performance through evaluation of its output impedance. This analysis method has been verified through simulation and experimentation. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among several switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based dc-dc converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional magnetic-based converter for medium to high conversion ratios.

Double-Tiered Switched-Capacitor Battery Charge Equalization Technique

Abstract: The automobile industry is progressing toward hybrid, plug-in hybrid, and fully electric vehicles in their future car models. The energy storage unit is one of the most important blocks in the power train of future electric-drive vehicles. Batteries and/or ultracapacitors are the most prominent storage systems utilized so far. Hence, their reliability during the lifetime of the vehicle is of great importance. Charge equalization of series-connected batteries or ultracapacitors is essential due to the capacity imbalances stemming from manufacturing, ensuing driving environment, and operational usage. Double-tiered capacitive charge shuttling technique is introduced and applied to a battery system in order to balance the battery-cell voltages. Parameters in the system are varied, and their effects on the performance of the system are determined. Results are compared to a single-tiered approach. MATLAB simulation shows a substantial improvement in charge transport using the new topology. Experimental results verifying simulation are presented.

A New Design Method for High-Power High-Efficiency Switched-Capacitor DC–DC Converters

Abstract: Switched-capacitor technology is widely used in low power dc-dc converter, especially in power management of the integrated circuit. These circuits have a limitation: high pulse currents will occur at the switching transients, which will reduce the efficiency and cause electromagnetic interference problems. This makes it difficult to use this technology in high-power-level conversion. This paper presents a new design method for dc-dc converter with switched-capacitorldquo technology. The new method can reduce the high pulse current which usually causes serious problem in traditional converters. Therefore, the power level of this new designed converter can be extended to 1 kW or even higher. A 1-kW 42/14-V switched-capacitor converter was designed for 42-V automotive system. The proposed converter has no requirement for magnetic components and can achieve a peak efficiency of 98% and 96 % at full load. The main circuit of the dc-dc converter is analyzed and its control scheme is presented in the paper. The experimental results verified the analysis and demonstrate the advantages.

Merged two-stage power converterarchitecture with softcharging switched-capacitor energy transfer

Abstract: This paper presents a two-stage architecture that combines a large step-down switched-capacitor transformation stage with a high-bandwidth magnetic regulation stage. The proposed design is particularly well-suited for an integrated CMOS process, as it makes use of the available on-die device characteristics. In such a process, the two-stage architecture presented offers high efficiency, high power density, and high- bandwidth regulation. We show that by merging the switched-capacitor stage and the regulation stage in a specific manner, further performance improvements can be attained. When the fast-switching regulation stage is used to provide soft charging of the switched-capacitor stage, a substantial improvement in performance is possible. An experimental prototype, implemented using discrete components, validates the approach.

A 65nm Sub-V t Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter

Abstract: This paper presents a 65nm sub-Vt SoC featuring a microcontroller core and custom 128Kb SRAM functional in sub-threshold, powered by a switched capacitor DC-DC converter that delivers variable load voltages from 0.3V to 0.6V.

Nanoscale memory cell based on a nanoelectromechanical switched capacitor.

Abstract: The demand for increased information storage densities has pushed silicon technology to its limits and led to a focus on research on novel materials and device structures, such as magnetoresistive random access memory and carbon nanotube field-effect transistors, for ultra-large-scale integrated memory. Electromechanical devices are suitable for memory applications because of their excellent 'ON-OFF' ratios and fast switching characteristics, but they involve larger cells and more complex fabrication processes than silicon-based arrangements. Nanoelectromechanical devices based on carbon nanotubes have been reported previously, but it is still not possible to control the number and spatial location of nanotubes over large areas with the precision needed for the production of integrated circuits. Here we report a novel nanoelectromechanical switched capacitor structure based on vertically aligned multiwalled carbon nanotubes in which the mechanical movement of a nanotube relative to a carbon nanotube based capacitor defines 'ON' and 'OFF' states. The carbon nanotubes are grown with controlled dimensions at pre-defined locations on a silicon substrate in a process that could be made compatible with existing silicon technology, and the vertical orientation allows for a significant decrease in cell area over conventional devices. We have written data to the structure and it should be possible to read data with standard dynamic random access memory sensing circuitry. Simulations suggest that the use of high-k dielectrics in the capacitors will increase the capacitance to the levels needed for dynamic random access memory applications.

Voltage-Balancing Circuit Based on a Resonant Switched-Capacitor Converter for Multilevel Inverters

Abstract: This paper proposes a new voltage-balancing circuit for the split dc voltages in a diode-clamped five-level inverter. The proposed circuit is based on a resonant switched-capacitor converter (RSCC), which consists of two half-bridge inverters, a resonant inductor, and a resonant capacitor. A new phase-shift control of the RSCC is proposed to improve voltage-balancing performance. As a result, it is possible to reduce the inductor to one tenth in volume as compared to a conventional voltage-balancing circuit based on a buck-boost converter. Experimental results are shown to verify the viability of the RSCC-based voltage-balancing circuit.

High Conversion Ratio DC–DC Converters With Reduced Switch Stress

Abstract: In this paper, a new class of single-switch nonisolated high step-up DC-DC converters with simple topologies is proposed. The proposed topologies utilize a hybrid switched capacitor technique for providing a high voltage gain without extreme switch duty cycle and yet enabling the use of a lower voltage and RDS-ON MOSFET switch so as to reduce cost, switch conduction and turn-on losses. Other advantages of the proposed topologies include: continuous input/output current, simple structure and control. The principle of operation in continuous conduction mode and discontinuous inductor current mode are analyzed. Experimental results obtained on a 45-W prototype are also presented.

Self tuning pick-ups for inductive power transfer

Abstract: Inductive power transfer systems are now commonly used in ultra clean or dirty industrial applications to deliver power to both moving and stationary loads without contact. Each load requires a power pick-up and regulator that is coupled to a track, which carries a resonant current at VLF frequencies (typically 10-50 kHz). Modern pick-ups are tuned for resonance at the track frequency and their power delivery increasingly depends on accurate tuning of the resonant circuit. In this paper a new self tuning power regulator for inductive power transfer systems is proposed and a control strategy described. The system uses a binary weighted series of capacitors that can be switched via simple relays across a parallel resonant pick-up circuit. There are no additional switching losses during tuning, detection and operation so that the technique is applicable to high power pick-ups. The tuning circuit is evaluated under simulation and then made to operate on a practical 500 W pick-up regulator used in materials handling applications. In both simulation and experiment it is shown to successfully detect the tuning state of the system and correct for it during operation.

Control Schemes for DC Capacitor Voltages Equalization in Diode-Clamped Multilevel Inverter-Based DSTATCOM

Abstract: This paper examines the application of a diode-clamped multilevel inverter (DCMLI)-based distribution static compensator (DSTATCOM) connected to a three-phase, four-wire (3p4w) distribution system. The DCMLI has an inherent unbalancing problem among its DC capacitor voltages. Additionally, when the load contains a DC part, the neutral point of the compensator also becomes unbalanced. In this paper, the effects of different loading conditions on the DC capacitor voltages of the inverter are studied. Two new control circuits are proposed for equalizing the capacitor voltages. Different control techniques are presented for the equalizing circuits. Equations of the proposed equalizing controllers are developed corresponding to the control of the switching devices. Comparative studies of different control techniques and the performances of the two controllers are performed. Simulation studies are performed using PSCAD/EMTDC to validate the efficacy of the proposed equalizing controller circuits.

High power resonant Switched-Capacitor step-down converter

Abstract: This paper treats a new type of high power switched-capacitor-DC-DC-converter (SCDDC), which is characterized by resonant switching transitions. This drastically reduces switching losses and opens up the possibility to employ thyristors instead of turn-off power semiconductors. At the same time a larger energy can be transferred per switching cycle and/or the application of the SCDDCs can be extended into the megawatt power range. For operation with high switching frequency thyristors are replaced by IGCTs which allow to avoid a turn-off time in reverse-blocking mode. The new converter topology is extensively analyzed using simulations. To gain practical results a small scale prototype is designed and the operation of the proposed converter is experimentally verified including the resonant operation of IGCTs which results in significantly reduced switching losses.

Features and Design Constraints for an Optimized SC Front-End Circuit for Capacitive Sensors With a Wide Dynamic Range

Abstract: This paper presents optimization criteria for an integrated switched-capacitor front-end circuit for capacitive sensors with a wide dynamic range. The principle of the interface is based on the use of a relaxation oscillator. A negative-feedback circuit controls the charge-transfer speed to prevent the overload of the input amplifier for large input signals which thus enables a wide dynamic range of capacitor values. Moreover, it has been shown that the use of negative feedback can also result in much better noise performance. However, for the interface to function properly, there is a serious limitation for the value of a specific parasitic capacitance. Therefore, a method which extends the acceptable range of this parasitic capacitance is proposed. A novel method of linearity measurement which takes the influence of PCB parasitic capacitances into account, is also presented. The circuit has been designed and implemented in 0.7 mum standard CMOS technology. The supply voltage is 5 V and the measured value for the supply current is about 1.4 mA. Experimental results show that for the capacitor range of 1 pF to 300 pF, application of negative feedback yields a linearity of about 50 x10-6 (14 bits) with a 16-bit resolution for a measurement time of 100 ms. Tests have been performed over the temperature range from to .

ZVT Interleaved Boost Converters with Built-In Voltage Doubler and Current Auto-Balance Characteristic

Abstract: An interleaved boost converter with coupled inductors and switched capacitors is proposed in this paper. The switched capacitors are used to realize the inherent voltage-double function that increases the voltage gain and reduces the voltage stress of the switch greatly. Therefore, the low-conduction resistance and low-voltage-rated switches can be applied to improve the efficiency of this topology. Moreover, the load current can automatically be equally shared by each phase as a consequence of the switched capacitors adopted in the output stage. Active clamp circuits are applied for the interleaved two phases to recycle the leakage energy and absorb the voltage spikes caused by the leakage inductance. Both the main and the clamping switches are zero-voltage transition (ZVT) switches during the whole switching transition that reduce the switching losses. The current falling rates of the clamping diodes and output diodes are controlled by the leakage inductance so that the diode reverse-recovery problem is alleviated. The experimental results are shown to verify the effectiveness of the theoretical analysis based on a 48- to- 380-V DC/DC prototype.

A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique

Abstract: Previously reported multi-bit oversampling DeltaSigma audio DACs use 2-level (+1, -1) unit elements in either switched-capacitor or current-steering form. This paper presents a low-power audio DAC that uses a 3-level current-steering unit element architecture.

A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference

Abstract: We have developed a switched-capacitor CMOS voltage reference (SCVR). The circuit is shown in Fig. 24.3.2 and is composed of a low-power bias circuit [G. De Vita and G. iannacone, 2007], a core circuit and a switched-capacitor difference amplifier that is insensitive to op-amp offset voltage. The clock signals (phi1, phi2, phi2') are non-overlapping to prevent leakage. The core circuit supplies Vgs1 and Vgs2 to the switched-capacitor difference amplifier on phases phi1 and phi2, respectively. The difference amplifier then generates an output, which has a low TC, based on the gate-source voltage difference, AVGS.

Component-Efficient Multiphase Switched-Capacitor DC–DC Converter With Configurable Conversion Ratios for LCD Driver Applications

Abstract: A CMOS 3/4-phase switched capacitor dc-dc converter with configurable conversion ratios of 4 times /5 times /6 times /7times is proposed for liquid crystal display driver applications. The 3/4-phase driving scheme requires only 3 off-chip flying capacitors and 5 package pins. The converter core, input voltage monitor, 3/4-phase clock generator and bandgap voltage reference were integrated using a 0.35-mum high-voltage CMOS process. The input voltage ranges from 2.5 to 5 V, and the output voltage is higher than 15 V with a load current of 500 muA. Measurement results confirmed the validity and performance of the driving scheme.

Multi-mode switched capacitor dc-dc voltage converter

Abstract: The disclosure describes techniques for converting an input voltage level to two or more output voltage levels using only two pump capacitors and three switching phases. The disclosure also describes techniques for selectively controlling a dc-dc converter to operate in different conversion modes. One mode may use only two pump capacitors and three switching phases to produce output voltage levels with a first set of conversion ratios. Another mode may use two pump capacitors and two switching phases to produce output voltage levels with a second set of conversion ratios. The first mode may use three different subcircuit arrangements of the pump capacitors. The second mode may use two different subcircuit arrangements of the pump capacitors. A converter may include switches and pump capacitors that can be selectively configured to transition between two or three different subcircuits, thereby producing output voltages according to different conversion ratios on a selective basis.

A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applications

Abstract: This letter presents the design and experimental results of a 1.8/2.14 GHz dual-band CMOS low-noise amplifier (LNA), which is usable for code division multiple access and wideband code division multiple access applications. To achieve the narrow-band gain and impedance matching at both bands, an extra capacitor in parallel with the Cgs of the main transistor and a harmonic tuned load are switched. Except for the output blocking capacitor and series inductor, all components are integrated on a single-chip. The LNA is designed using a 0.13mum- CMOS process and employs a supply voltage of 1.5 V and dissipates a dc power of 7.5 mW. The measured performances are gains of 14.54 dB and 16.6 dB, and noise figures of 1.75 dB and 1.97 dB at the two frequency bands, respectively. The linearity parameters of and P1dBin are -16dBm and -5.8 dBm at the 1.8 GHz, -14.8 dBm and -5.3 dBm at the 2.14 GHz, respectively.

Robust Multiple-Phase Switched-Capacitor DC–DC Power Converter With Digital Interleaving Regulation Scheme

Abstract: An integrated switched-capacitor (SC) DC-DC converter with a digital interleaving regulation scheme is presented. By interleaving the newly-structured charge pump (CP) sub-cells in multiple phases, the input current ripple and output voltage ripple of the converter are reduced significantly. The converter exhibits excellent robustness, even when one CP sub-cell fails to operate due to unexpected device failure. A fully digital controller is employed with hysteretic control, featuring deadbeat stability and fast transient response. With a 1.5-V input power supply, the SC power converter precisely provides an adaptable regulated power output from 1.6 to 2.7 V. A maximum output ripple of plusmn20 mV is observed at the full load of 540 mW. The load transient response is around 1.8 mus, when the load current switches from half to full load (from 100 to 200 mA). The design provides a fast-response, low-noise, and fault-tolerant solution to new-generation on-chip power supplies.

Adaptive-gain step-up/down switched-capacitor dc/dc converters

Abstract: A switched-capacitor DC-DC converter has a reconfigurable power stage with variable gain ratio and/or interleaving regulation for low ripple voltage, fast load transient operation, variable output voltage and high efficiency. Since the power stage has multiple switches per capacitor, the converter exploits reconfigurable characteristics of the power stage for fast dynamic control and adaptive pulse control for tight and efficient voltage regulation.

On performance limits of switched-capacitor multi-phase charge pump circuits. Remarks on papers of Starzyk et al.

Abstract: Important contributions on multi-phase charge pumps of Starzyk et al posed a question about a maximum voltage gain in a circuit containing k capacitors. We comment on Starzyk's conjecture of 2k-1 gain and give general limit value theorems. We conclude that Starzykpsilas conjecture is true however, in general terms it gives a condition that is necessary but not sufficient. A note on circuit realizations is given.

Optimal PWM Control of Switched-Capacitor DC–DC Power Converters via Model Transformation and Enhancing Control Techniques

Abstract: This paper presents an efficient and effective method for an optimal pulsewidth-modulated (PWM) control of switched-capacitor dc-dc power converters. Optimal switching instants are determined based on minimizing the output ripple magnitude, the output leakage voltage and the sensitivity of the output load voltage with respect to both the input voltage and the load resistance. This optimal PWM control strategy has several advantages over conventional PWM control strategies: 1) it does not involve a linearization, so a large-signal analysis is performed; and 2) it guarantees the optimality. The problem is solved via both the model transformation and the optimal enhancing control techniques. A practical example of the PWM control of a switched-capacitor dc-dc power converter is presented.

Integration of switched capacitor networks for power delivery

Abstract: Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module.

Switched-capacitor regulators

Abstract: A switched-capacitor regulator is provided for regulating the output voltage of a voltage supply. The switched-capacitor regulator includes a supply input terminal capable of receiving a supply voltage, two or more flying capacitors, a regulation switch located between each flying capacitor and the supply input terminal, and a voltage control circuit. The activity of the regulation switches is controlled by the voltage control circuit. In one embodiment of the invention, the voltage control circuit includes a feedback resistance area having one or more feedback resistors located between the output of the flying capacitors and a ground terminal, a first gain stage connected to the feedback resistance area, and two or more second switchable gain stages, which are each connected to a regulation switch and the first gain stage. The switched-capacitor regulator operates in pseudo-continuous regulator mode using three-stage switchable operational amplifiers with time-multiplexed pole-splitting compensation.

On Two Fundamental Signatures for Determining the Relative Location of Switched Capacitor Banks

Abstract: This paper describes two fundamental signatures of shunt capacitor bank switching transient phenomena from which one can accurately determine the relative location of an energized capacitor bank whether it is upstream or downstream from the monitoring location. Mathematical analysis of a capacitor bank energizing proves that: 1) the energized capacitor bank affects only the upstream reactive power flow and 2) at the energizing instant, the gradients (time derivatives) of voltage and current waveforms measured upstream from the capacitor location will have opposite signs. The reverse is true in that at the energizing instant, gradients of voltage and current waveforms measured downstream from the same capacitor location will have equal signs. Thus, we can precisely determine the relative location of the switched capacitor bank by simply evaluating power factor changes and the signs of voltage and current waveform gradients at the switching instant. The efficacy of our practical direction-finding technique is demonstrated analytically and by way of time-domain simulation models and actual data.

A 4–6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link

Abstract: A wide range differentially tuned LC PLL using dual switched capacitor VCOs was designed in a 65 nm standard CMOS process for a forwarded clock link. Bandwidth and stability were maintained across the operating range by using open-loop auto frequency calibration (AFC) tuning techniques and an adaptively biased bit-sliced charge pump. The PLL is capable of supporting spread spectrum clock (SSC) modulation with a low peak VCO gain by limiting its operation to the high gain region of the varactors where the capacitance versus voltage curves exhibit the greatest linearity. The VCOs support a frequency range of 4.0-4.8 GHz and 5.87-6.4 GHz. The 2-UI jitter of the forwarded clock at 6.4 Gb/s is 0.9 ps RMS while the long term acumulated N-UI jitter for large N is 2.1 ps RMS.

Solar powered battery charger using switch capacitor voltage converters

Abstract: The invention provides a charging device that uses switched capacitor voltage converters to charge a battery using solar power. The charger uses boosting topology to efficiently use solar module photovoltaic power. The boosting topology enables a lower voltage to be used resulting in reduced cutting and soldering of photovoltaic cells. The battery charger has overcharge protection and uses inductor-less circuitry.

Area-driven optimisation of switched-capacitor DC/DC converters

Abstract: Popular capacitive DC/DC converter topologies are optimised and compared towards the total required capacitance. The analysis shows that from an area point of view the series-parallel, Fibonacci and Dickson topologies perform equally. The voltage doubler topology is proven to be inferior.

A Third-Order 9-Bit 10-MHz CMOS $\Delta \Sigma $ Modulator With One Active Stage

Abstract: We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.