Showing papers on "Thin-film transistor published in 1992"

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

Abstract: The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.

Semiconductor memory device and method of formation

Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

Method for forming a MOS transistor and structure thereof

Abstract: A method for forming a MOS transistor having LDD structure by a simple and a few number of processes and a structure thereof are described. In accordance with the present invention, a low concentration of an impurity region can be formed in a semiconductor film part between an end of gate electrode and source or drain, by forming an ordinary gate insulating film extending beyond the gate electrode in the direction along the source and drain, in place of a spacer in the side of gate electrode which has been required for a preparation of conventional TFT having LDD structure, and further by forming a thinner insulating film than the gate insulating film in the side thereof, and by utilizing the thickness difference between the gate insulating film part excepting the gate electrode and the thin insulating film in the side thereof.

Thin film transistor and semiconductor device including a laser crystallized semiconductor

Abstract: A semiconductor material and a method for forming the same, the semiconductor material having fabricated by a process comprising irradiating a laser beam or a high intensity light equivalent to a laser beam to an amorphous silicon film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×10 19 atoms·cm -3 or lower, preferably 1×10 19 atoms·cm -3 or lower, without melting the amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, the semiconductor materials being useful for fabricating compact thin film semiconductor devices such as thin film transistors improved in device characteristics.

Semiconductor memory device

Abstract: PURPOSE:To further enhance the degree of higher integration by consisting a gate electrode of a thin film transistor, a channel formation layer, a power source terminal, and connection patterns of each word transistor to bit lines by a metal layer with polycrystal silicon layers from the first to the fourth CONSTITUTION:Under lamination structure adopted herein, a first polycrystal silicon 11 to a fourth polycrystal silicon layer 14 and a conductive layer 15 are laminated In the first polycrystal silicon layer 11, each gate electrode for switching transistors Q3 and Q4 are installed on each semiconductor base board 1 On the first to the fourth polycrystal silicon layers 12 to 14, one of the respective polycrystal silicon layers form gate electrodes GT1 and GT2 for thin film transistors TFT1 and TFT2 while one of the respective polycrystal semiconductor layers form a channel formation layer 15 for these transistors TFT1 and TFT2 Other polycrystal silicon layer forms a power source terminal VSS while a metal layer 15 forms a connection pattern of each work transistor Q1 and Q2 for bit caps B1 and B2 This construction makes it possible to enhance a higher degree of integration

Method of making a MOS thin film transistor with self-aligned asymmetrical structure

Abstract: A semiconductor thin film formed over a substrate and having drain and source regions each being of a conductivity type and a channel region of another conductivity type defined between the drain and source regions, a gate electrode(s) formed over and/or below the channel region of the semiconductor thin film through an insulating layer(s), a pair of electrodes being connected to the drain and source regions of the semiconductor thin film, in which said source region is placed in a self-aligned manner and adjoined to said channel region, while a drain-offset region is defined between said channel region and said drain region in a self-aligned manner.

Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures

Abstract: Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5- mu m-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO/sub 2/ interface roughness scattering are the main factors in determining the transistor performance. >

In-Situ Chemically Cleaning Poly-Si Growth at Low Temperature

Abstract: We report a novel growth method of polysilicon thin films on glass substrates at a low temperature (450°C) by plasma chemical vapor deposition (PCVD) using SiH4/SiF4 mixture gases. In this method, the conventional low-cost glass substrates such as Corning 7059 may be used because of the low deposition temperature. Furthermore, the conventional vacuum chamber with its base pressure of ~1×10-4 Pa, which is usually thought to be inadequate for high-quality Si growth because of its many impurities, can be used since the growing surface of polysilicon is in-situ chemically cleaned by SiF4 plasma. The polysilicon films obtained on glass show strong (100) preferred orientation. A grain size as large as 250 nm is obtained in a film with 700 nm thickness. The field-effect mobility of 44 cm2/Vs has been achieved in a thin-film transistor (TFT) using this polysilicon film.

Thin-film transistor

Abstract: PURPOSE:To prevent the deterioration of an on current with lapse of time and the change of a threshold voltage with lapse of time by providing an impurity semiconductor layer having the conduction type reverse from the conduction type of source and drain electrodes so as to cover the whole or part of channel parts and to come into contact with the substrate side boundary of the channel layers CONSTITUTION:A substrate 101 is a glass substrate or quartz substrate having light transmissivity and process heat resistance The layer to the directly deposited on the substrate 101 is P type polysilicon which is patterned to an island shape and is formed as a base layer 102 The nearly intrinsic polysilicon layer deposited in contact with the base layer 102 is also patterned on the inner side of the base layer and is formed as the channel layer 103 This patterning is executed for shielding the substrate side of the channel layer with the base layer and prevents the conduction by the photocurrent of the source and drain electrodes and the channel parts are simultaneously light- shielded at this time The base layer 102 is provided in such a manner The deterioration of the on-current with lapse of time and the change of the threshold voltage with lapse of time are prevented

Polysilicon TFT circuit design and performance

Abstract: Both n- and p-channel polysilicon TFTs can be fabricated, allowing CMOS circuit techniques to be used. However, TFT characteristics are poor in comparison to conventional single-crystal MOSFETs, and relatively coarse design rules must be used to be compatible with processing on large-area glass plates. The authors examine these issues and describe the performance of a range of digital and analog circuit elements built using polysilicon TFTs. Digital circuit speeds in excess of 20 MHz are reported, along with operational amplifiers with over 80 dB of gain and more than 1-MHz unity-gain frequency. Several polysilicon TFT switched-capacitor circuits are also reported and shown to have adequate linearity, output swing, and settling time to form integrated data line drivers on an active-matrix liquid crystal display. >

Modeling of amorphous-silicon thin-film transistors for circuit simulations with SPICE

Abstract: A static and dynamic model for amorphous silicon thin-film transistors is presented. The theory is based on an assumed exponential distribution of the deep states and the tail states in the energy gap. Expressions are derived that link the density of the localized states and the temperature to the drain current and the distribution of the charge in the transistor channel. In addition the authors take into account parasitic effects such as channel length modulation, off-resistance, drain and source resistances, mobile and free charges in the insulator, surface states, and overlap capacitances. The model is incorporated into the circuit simulation program SPICE. Charge conservation problems are overcome by using a charge-oriented dynamic transistor model. Simulated and measured current-voltage characteristics agree well. A 96-b gate line driver for addressing liquid-crystal displays, which was successfully designed and optimized with the model, is introduced. >

Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin-Film Transistors

Abstract: It has been confirmed that the leakage current observed in Metal-Oxide-Semiconductor (MOS) transistors and polycrystalline thin-film transistors (poly-Si TFTs) corresponds to activation energies of the current. Two new models of the conduction of leakage current have been proposed on the basis of this correspondence. These models consist of two types of steps: the first step is the thermal emission of an electron occurring in the neighborhood of the drain electrode, and the second step is the tunneling of an electron through a trap state in the band gap. These models have enabled us to explain the conduction mechanism of the leakage current in various devices.

Semiconductor device having a thin-film transistor and process

Abstract: A semiconductor device having a thin-film transistor (22) and a process for making the device. The semiconductor device includes a substrate (11) having a principal surface. A gate electrode (29) overlies the principal surface and a gate dielectric layer (23) overlies the gate electrode (29). A conductive channel interface layer (25) overlies the upper surface of the gate electrode (29) and is spaced apart from the gate electrode (29) by the gate dielectric layer (23). A conductive thin-film layer (57) overlies the gate electrode (29) and forms a metallurgical contact to the channel interface layer (25). Remaining portions of the thin-film overlie the principal surface and form source and drain regions (63, 65) of the thin-film transistor (22). The thin-film source and drain regions (63, 65) are formed by placing a diffusion barrier cap (60) over the channel portion (61) of the thin-film layer (57) and introducing conductivity determining dopant into the thin-film layer (57). A silicide is formed in the thin-film source and drain regions (63, 65) by the depositing a refractory metal layer over the thin-film layer (57) and the diffusion barrier cap (60) and annealing the thin-film layer (57).

Manufacture of semiconductor device

Abstract: PURPOSE:To facilitate selection and control within a range, in which ions are not implanted, by equalizing the width of a sidewall film and the film thickness of a coated film when a stepped section is generated in the coated film deposited by the stepped section of a gate electrode section, the coated film is etched in an anisotropic manner and the sidewall film is formed. CONSTITUTION:Boron ions are implanted using a gate electrode 5 as a mask, and a P region 13 is formed in a polycrystalline silicon film 3 and an oxide film 10 of specified thickness is deposited. An oxide film pattern 11 is formed at a place, where the estimated maximum misalignment (a) is taken into consideration, and the oxide film pattern 11 is etched in an anisotropic manner while employing a nitride film 9 as a stopper from the state, thus shaping a sidewall film 12. The nitride film 9 is removed through etching, boron ions are implanted for forming source-drain diffusion layers in a P diffusion layer region, thus forming a P diffusion layer. The quantity of the offset of a TFT can be formed at a constant value regardless of the misalignment of a photoresist and the accuracy of finishing, thus allowing the inhibition of the variation of characteristics, thus stable performance characteristics are achieved.

Plasma-Enhanced Chemical Vapor Deposition of Silicon Nitride

Abstract: The optimum condition of plasma-enhanced chemical vapor deposition to deposite silicon nitride (SiNx) film and its application as a gate insulator of a-Si thin-film transistor (TFT) have been investigated. The internal stress of SiNx in the range of 4.3×109 dyn/cm2 tensile to 8.0×109 dyn/cm2 compressive is found to be controllable by changing the ratio of H2 and N2 in the source gases without affecting the optical band gap. Satisfactory TFT characteristics and high reliability are realized by using a gate insulator of SiNx having either stoichiometric or N-rich composition which shows the large optical band gap.

Liquid crystal display device with a capacitor and a thin film transistor in a trench for each pixel

Abstract: A liquid crystal display device includes a pair of opposed insulating substrate and a liquid crystal layer sandwiched therebetween. One of the insulating substrates is formed with a first trench for forming a thin film transistor therein and a second trench for forming a capacitor element therein. The thin film transistor is constituted of a semiconductor layer formed along an inner surface of the first trench, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer. The capacitor element is constituted of a first electrode formed along an inner surface of the second trench, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer. The first electrode is formed integrally with the semiconductor layer, thereby increasing an aperture ratio. The first trench has a tapering side surface, thereby ensuring uniform ion implantation for the semiconductor layer. In the case that the substrate has a laminated structure of an insulating substrate and an insulating layer, an etching rate of the substrate as a whole can be improved.

Method of manufacturing a thin film transistor

Abstract: Source (51) and drain (52) of a thin-film transistor (TFT) are formed from a conductive layer (5) using a photolithographic step (FIG. 3) in which the gate (4) serves as a photomask. In accordance with the invention the insulated gate structure (3,4) is formed at the upper face of the channel-forming semiconductor film (2), i.e. remote from the transparent substrate (1). The semiconductor film (2) may be annealed to high-mobility polycrystalline material before depositing the gate structure (3,4) and the overlying conductive layer (5). In this way, high speed TFTs can be formed due to a combination of low gate-to-drain and gate-to-source capacitances and the provision of the transistor channel in the high quality semiconductor material adjacent to the upper face of the film (2). Preferably ultra-violet radiation (20: FIG. 1) is used for the annealing with an absorption depth less than the thickness of the film (2) so that the film-substrate interface is not heated which otherwise may weaken the adhesion of the film (2) to the substrate (1). By using an angled exposure in a photolithographic and etching step with the gate (4) as a shadow photomask, a low-doped drain part can be defined from a conductive layer (5) comprising highly-doped material on low-doped material. This low-doped drain part reduces the effect of high drain bias in operation of the TFT.

Method for making a self-aligned vertical thin-film transistor in a semiconductor device

Abstract: A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).

Thin film transistor device for driving circuit and matrix circuit

Abstract: In the case of an LDD-structure thin film transistor, an on-current becomes large as impurity concentration of low level impurity source and drain regions is increased. Then, when the impurity concentration is increased to a first impurity concentration, the on-current reaches to a substantially maximum point. On the other hand, a cut-off current Ioff becomes substantially minimum when the impurity concentration is decreased to a second impurity concentration. The cut-off current is gradually increased even if the impurity concentration becomes higher or lower than the second impurity concentration. Therefore, impurity concentration of low level impurity source and drain regions (22b) of a thin film transistor (14) for a peripheral circuit is set to a first impurity concentration, and that of low concentration impurity source and drain regions (21b) of a thin film transistor (12) for a matrix circuit is set to a second impurity concentration.

Water-related instability in TFTs formed using deposited gate oxides

Abstract: Polycrystalline silicon thin film transistors formed with undensified gate oxides have shown instability phenomena not observed for TFTS formed with oxides annealed at 600 degrees C or above. These instabilities are related to ionized water in the oxide, with positive (H+) and negative (OH-) ions drifting on the application of gate bias to produce both negative and positive threshold voltage shifts. The mobility for the OH- ions is found to be lower than that for the H+ ions, as might be expected. In addition, kinks in the subthreshold characteristic are sometimes seen, and these are shown to be due to a sidewall effect. The water diffuses in from the atmosphere laterally under the gate electrode, and this gives rise to a gate length dependence of the effects. From this dependence a diffusion coefficient approximately 3*10-12 cm2 s-1 is deduced at room temperature. This is some eight orders of magnitude higher than that for fused silica, and confirms the porosity of the material.

Drastic Enlargement of Grain Size of Excimer-Laser-Crystallized Polysilicon Films

Abstract: Polysilicon thin films with extremely large grains (grain size more than 50 µm, i.e., three orders of magnitude more than the typical value) have been formed using an excimer-laser crystallization method for the first time. This drastic enlargement was achieved by the reduction of the solidification rate of molten silicon by the small heat capacitance effect of the thin silicon-dioxide membrane used as a substrate. Crystallinity and film properties have been evaluated from Raman spectroscopy, resistivity, Hall effect and transistor characteristics. The Hall mobility of electrons was as high as 610 cm2/Vs.

Thin-film transistor matrix device and its production

Abstract: PURPOSE: To provide the novel thin-film transistor(TFT) matrix device which can decrease the damages of an insulating film for storage capacities in an etching stage at the time of forming the TFTs and the process for production of the device. CONSTITUTION: This TFT matrix device has a gate electrode layer 11 connected to gate bus lines, a gate insulating layer 12 laminated on the gate electrode layer, a semiconductor layer 13 including an active layer disposed in contact with the gate insulating layer and a pair of contact layers thereon, a protective film 14 covering the active layer of the semiconductor layer, a source electrode layer 16 connecting one of the contact layers to signal bus lines and a drain electrode layer 17 connecting the other of the contact layers to picture element electrodes 18. The device has an insulating layer 22 constituting the layer common with the gate insulating layer on the storage capacity electrodes in the intersected regions of the storage capacity electrodes 21 and the picture element electrodes and a protective layer 24 which is disposed thereon and constitute the layer common with a part of the other layer forming the TFTs. COPYRIGHT: (C)1993,JPO&Japio

Improving the uniformity of poly-si films using a new excimer laser annealing method for giant-microelectronics

Abstract: Film uniformity is the main problem when applying laser-recrystallised poly-Si films to thin film transistors (TFTs) in giant micro electronics. However, this has been dramatically improved by a new excimer laser annealing method in which the solidification process of molten Si is controlled by low-temperature (400°C) substrate heating during excimer laser annealing. Poly-Si TFT fabricated around the laser irradiation overlap region exhibited a high field effect mobility uniformity of within ±8%.

Bias-stress-induced creation and removal of dangling-bond states in amorphous silicon thin-film transistors

Abstract: We report on the threshold voltage shift in amorphous silicon thin‐film transistors, subjected to a gate bias for a prolonged period of time (bias stress). For transistors made with a silicon nitride gate insulator, the threshold voltage shift for low positive bias is due to dangling‐bond‐state creation in the amorphous silicon layer. For low negative bias, the threshold voltage shift is due to the bias‐stress‐induced removal of dangling‐bond states. These results are contrasted with previously published results for oxide transistors, but both results are consistent with a defect pool model for the dangling‐bond states. The difference for oxide and nitride transistors is due to a different zero‐bias Fermi energy position at the interface. For nitride transistors at much larger applied bias, the dominant mechanism changes and the threshold voltage shift is dominated by charge trapping in the gate dielectric. This is found for both large negative and large positive bias.

Process for formation of delta-doped quantum well field effect transistor

Abstract: A process for formation of a delta-doped quantum well field effect transistor is disclosed, and the transistor includes: a substrate, a super lattice, a buffer layer, quantum wells, a cap layer, and an ohmic layer. Then a drain, a source and a gate are formed on the ohmic layer. Each of the quantum wells is formed in such a manner that: a first GaAs layer is formed by applying a metalorganic chemical vapor deposition process under a low reaction pressure; then an Si impurity such as SiH4 or Si2H6 is delta-doped into the layer; and then, a second GaAs layer is formed by applying the metalorganic chemical vapor deposition process under the same condition, thereby forming the GaAs/AlGaAs delta-doped quantum well field effect transistor of the present invention, having the advantage of economy.

Method for manufacturing a semiconductor device and a semiconductor memory device

Abstract: An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Low-temperature (<or=550 degrees C) fabrication of poly-Si thin-film transistors

Abstract: High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550 degrees C. This process features the use of polycrystalline Si/sub 0.5/Ge/sub 0.5/ for the gate material and high-dose H/sup +/ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm/sup 2//V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600 degrees C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates. >

CMOS device for use in connection with an active matrix panel

Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display

Abstract: A low-temperature poly-Si thin-film transistor (TFT), having inverted-staggered structure, has been developed successfully using excimer laser annealing and ion doping. This TFT is suitable for pixel transistors of large-area and high-resolution LCDs. The maximum process temperature of the TFT fabrication steps is less than 450°C, so the same glass substrate on which amorphous Si TFT arrays are formed can be used in this poly-Si TFT process. Furthermore, most of the procedures, equipment and thin-film materials used to fabricate amorphous Si TFTs are compatible with fabrication of the poly-Si TFTs. On the other hand, some investigation of the CMOS driver circuit has been done, and it has been found that the threshold voltage of these poly-Si TFTs can be controlled easily by lightly doping of B ion into the channel region using the ion doping system.