Showing papers on "Very-large-scale integration published in 1994"

Fat-trees: universal networks for hardware-efficient supercomputing

Abstract: The author presents a new class of universal routing networks, called fat-trees, which might be used to interconnect the processors of a general-purpose parallel supercomputer. A fat-tree routing network is parameterized not only in the number of processors, but also in the amount of simultaneous communication it can support. Since communication can be scaled independently from the number of processors, substantial hardware can be saved for such applications as finite-element analysis without resorting to a special-purpose architecture. It is proved that a fat-tree of a given size is nearly the best routing network of that size. This universality theorem is established using a three-dimensional VLSI model that incorporates wiring as a direct cost. In this model, hardware size is measured as physical volume. It is proved that for any given amount of communications hardware, a fat-tree built from that amount of hardware can stimulate every other network built from the same amount of hardware, using only slightly more time (a polylogarithmic factor greater).

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Abstract: The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods. >

A survey of power estimation techniques in VLSI circuits

Abstract: With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

Power consumption estimation in CMOS VLSI chips

Abstract: Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%. >

Analog Vlsi: Signal and Information Processing

Abstract: CMOS analogue building blocks BiCMOS analogue building blocks sampled-data signal processing continuous-time signal processing current-mode signal processing analogue VLSI neural information processing data converters statistical modelling and simulation of analogue analogue CAD interconnects in analogue VLSI analogue VLSI design-for-test analogue integrated sensors.

An Analog VLSI System for Stereoscopic Vision

Abstract: Foreword. Preface. 1: Synthesis. 2: The Silicon Retina. 2.1. Anatomical Models. 2.2. Architecture of the Silicon Retina. 2.3. Photoreceptors. 2.4. Horizontal Cells. 2.5. Bipolar Cells. 2.6. Physical Constraints on Information Processing. 2.7. Emergent Properties. 3: The Silicon Optic Nerve. 3.1. Summary of Existing Techniques. 3.2. Address-Event Representation. 3.3. Model of Data-Transfer Timing Efficiency. 3.4. Data Transfer in One Dimension. 3.5. Two-Dimensional Retina--Receiver System. 3.6. Advantages of Address Events. 4: Stereopsis. 4.1. Stereocorrespondence. 4.2. Neurophysiology. 4.3. Stereocorrespondence Algorithms. 4.4. Stereocorrespondence Chip. 4.5. Experiments. 4.6. Stereocorrespondence as a Model of Cortical Function. 5: System. A: Simple Circuits. A.1. Transistors. A.2. Current Mirrors. A.3. Differential Pairs. A.4. Transconductance Amplifiers. A.5. Low-Pass Filter. A.6. Resistor. Bibliography. Index.

Design of residue generators and multioperand modular adders using carry-save adders

Abstract: Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computational element used to implement various operations in digital signal processing systems using RNS. A comprehensive study of new residue generators and MOMA's is presented. The design methods given here take advantage of the periodicity of the series of powers of 2 taken module A (A is a module). Four design schemes of the n-input residue generators mod A, which are best suited for various pairs of n and A, are proposed. Their pipelined versions can be clocked with the cycle determined by the delay of a full-adder and a latch. A family of design methods for parallel and word-serial, using similar concepts, is also given. Both classes of circuits employ new highly-parallel schemes using carry-save adders with end-around carry and a minimal amount of ROM and are well-suited for VLSI implementation. They are faster and use less hardware than similar circuits known to date. One of the MOMA's can be used to build a high-speed residue-to-binary converter based on the Chinese remainder theorem. >

Iddq Testing for CMOS VLSI

Abstract: It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC's. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X.

RICE: rapid interconnect circuit evaluation using AWE

Abstract: This paper describes the Rapid Interconnect Circuit Evaluator (RICE) software developed specifically to analyze RC and RLC interconnect circuit models of virtually any size and complexity RICE focuses specifically on the passive interconnect problem by applying the moment-matching technique of Asymptotic Waveform Evaluation (AWE) and application-specific circuit analysis techniques to yield large gains in run-time efficiency over circuit simulation without sacrificing accuracy Moreover, this focus of AWE on passive interconnect problems permits the use of moment-matching techniques that produce stable, pre-characterized, reduced-order models for RC and RLC interconnects RICE is demonstrated to be as accurate as a transient circuit simulation with hundreds or thousands of times the efficiency The use of RICE is demonstrated on several VLSI interconnect and off-chip microstrip models >

Statistical Estimation of the Switching Activity in Digital Circuitsy

Abstract: Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density. This paper presents a statistical simulation technique to estimate individual node transition densities. The strength of this approach is that the desired accuracy and confidence can be specified up-front by the user. Another key feature is the classification of nodes into two categories: regular- and low-density nodes. Regular-density nodes are certified with user-specified percentage error and confidence levels. Low-density nodes are certified with an absolute error, with the same confidence. This speeds convergence while sacrificing percentage accuracy only on nodes which contribute little to power dissipation and have few reliability problems.

Using heavy-ion radiation to validate fault-handling mechanisms

Abstract: Fault injection is an effective method for studying the effects of faults in computer systems and for validating fault-handling mechanisms. The approach presented involves injecting transient faults into integrated circuits by using heavy-ion radiation from a Californium-252 source. The proliferation of safety-critical and fault-tolerant systems using VLSI technology makes such attempts to inject faults at internal locations in VLSI circuits increasingly important. >

Performance analysis and optimization of asynchronous circuits

Abstract: Asynchronous/self-timed circuits are beginning to attract renewed attention as a promising means of dealing with the complexity of modern VLSI designs. Very few analysis techniques or tools are available for estimating their performance. We adapt the theory of generalized timed Petri-nets (GTPN) for analyzing and comparing asynchronous circuits ranging from purely control-oriented circuits to those with data dependent control. Experiments with the GTPN analyzer are found to track the observed performance of actual asynchronous circuits, thereby offering empirical evidence towards the soundness of the modeling approach. >

Fast Multiplication: Algorithms and Implementations

Abstract: This thesis investigates methods of implementing binary multiplication with the smallest possible latency. The principle area of concentration is on multipliers with lengths of 53 bits, which makes the results suitable for IEEE-754 double precision multiplication. Low latency demands high performance circuitry, and small physical size to limit propagation delays. VLSI implementations are the only available means for meeting these two requirements, but efficient algorithms are also crucial. An extension to Booth's algorithm for multiplication (redundant Booth) has been developed, which represents partial products in a partially redundant form. This redundant representation can reduce or eliminate the time required to produce "hard" multiples (multiples that require a carry propagate addition) required by the traditional higher order Booth algorithms. This extension reduces the area and power requirements of fully parallel implementations, but is also as fast as any multiplication method yet reported. In order to evaluate various multiplication algorithms, a software tool has been developed which automates the layout and optimization of parallel multiplier trees. The tool takes into consideration wire and asymmetric input delays, as well as gate delays, as the tree is built. The tool is used to design multipliers based upon various algorithms, using both Booth encoded, non-Booth encoded and the new extended Booth algorithms. The designs are then compared on the basis of delay, power, and area. For maximum speed, the designs are based upon a 0.6$\mu$ BiCMOS process using emitter coupled logic (ECL). The algorithms developed in this thesis make possible 53 x 53 multipliers with a latency of less than 2.6 nanoseconds @ 10.5 Watts and a layout area of 13mm$\sp2$. Smaller and lower power designs are also possible, as illustrated by an example with a latency of 3.6 nanoseconds @ 5.8 W, and an area of 8.9mm$\sp2$. The conclusions based upon ECL designs are extended where possible to other technologies (CMOS). Crucial to the performance of multipliers are high speed carry propagate adders. A number of high speed adder designs have been developed, and the algorithms and design of these adders are discussed. The implementations developed for this study indicate that traditional Booth encoded multipliers are superior in layout area, power, and delay to non-Booth encoded multipliers. Redundant Booth encoding further reduces the area and power requirements. Finally, only half of the total multiplier delay was found to be due to the summation of the partial products. The remaining delay was due to wires and carry propagate adder delays.

An Exact Algorithm for Selecting Partial Scan Flip-Flops

Abstract: We develop an exact algorithm for selecting flip-flops in partial scan designs to break all feedback cycles. The main ideas that allowus to solve this hard problemexactly for large, practical instances are - graph transformations, a partitioning scheme used in the branch and bound procedure, and pruning techniques based on an integer linear programming formulation of the minimum feedback vertex set (MFVS) problem.We have obtained optimum solutions for the ISCAS '89 benchmark circuits and several production VLSI circuits within reasonable computation time. For example, the optimal number of scan flip-flops required to eliminate all cycles except self-loops in the circuit s38417 is 374. This optimal solution was obtained in 32 CPU seconds on a SUN Sparc 2 workstation.

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm

Abstract: A VLSI implementation of the International Data Encryption Algorithm is presented. Security considerations led to novel system concepts in chip design including protection of sensitive information and on-line failure detection capabilities. BIST was instrumental for reconciling contradicting requirements of VLSI testability and cryptographic security. The VLSI chip implements data encryption and decryption in a single hardware unit. All important standardized modes of operation of block ciphers, such as ECB, CBC, CFB, OFB, and MAC, are supported. In addition, new modes are proposed and implemented to fully exploit the algorithm's inherent parallelism. With a system clock frequency of 25 MHz the device permits a data conversion rate of more than 177 Mb/s. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM or FDDI. >

RSYN: a system for automated synthesis of reliable multilevel circuits

Abstract: Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN. >

Parallel logic simulation of VLSI systems

Abstract: Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verification prior to fabrication, and as VLSI systems grow in size, the execution time required by simulation is becoming more and more significant. Faster logic simulators will have an appreciable economic impact, speeding time to market while ensuring more thorough system design testing. One approach to this problem is to utilize parallel processing, taking advantage of the concurrency available in the VLSI system to accelerate the logic simulation task.Parallel logic simulation has received a great deal of attention over the past several years, but this work has not yet resulted in effective, high-performance simulators being available to VLSI designers. A number of techniques have been developed to investigate performance issues: formal models, performance modeling, empirical studies, and prototype implementations. Analyzing reported results of these techniques, we conclude that five major factors affect performance: synchronization algorithm, circuit structure, timing granularity, target architecture, and partitioning. After reviewing techniques for parallel simulation, we consider each of these factors using results reported in the literature. Finally we synthesize the results and present directions for future research in the field.

A communication architecture tailored for analog VLSI artificial neural networks: intrinsic performance and limitations

Abstract: An architecture for interchip communication among analog VLSI neural networks is proposed. Activity is encoded in a neuron's pulse emission frequency. Information is transmitted through the non-arbitered, asynchronous access of pulses to a common bus. The impact of collisions when the bus is accessed by more than one user is investigated. The information-carrying capability is assessed and the trade-off between accuracy of the transmitted information and attainable dynamic range is brought out in terms of simple global parameters that characterize the application. It is found that the proposed architecture is well suited for the kind of communication requirements associated to neural computation systems. A coding scheme aimed at pushing the system towards its theoretical performance is also presented and evaluated. >

Hardware implementation of an artificial neural network using field programmable gate arrays (FPGA's)

Abstract: In this paper, the authors present a hardware implementation of a fully digital multilayer perceptron artificial neural network using Xilinx Field Programmable Gate Arrays (FPGAs). Each node is implemented with two XC3042 FPGAs and a 1 K/spl times/8 EPROM. Training is done offline on a PC. The authors have tested successfully the performance of the network. >

Time-domain macromodels for VLSI interconnect analysis

Abstract: This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects. >

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

Abstract: The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them. >

Geometric autogeneration of "hard" phase-shift designs for VLSI

Abstract: A method implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve conflicting phase assignments, and eliminate unwanted phase edges. This process allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm. The autogeneration of phase shift patterns around an existing circuit design is broken down into four major tasks: 1. Define areas that need a phase assignment; 2. Make a first pass phase assignment unique to each critical feature and define "runs" of interrelated critical features; 3. Propagation phase assignment through the "runs"; and 4. Design trim features.

Reliability of majority voting based VLSI fault-tolerant circuits

Abstract: The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the replicated circuit modules as well as the majority voting circuits to account for the fact that, in VLSI implementations, the majority voting circuits are constructed from components of the same reliability as those used to construct the circuit modules. From the fault injection simulation, a survivability distribution is obtained which, when combined with an area overhead expression, leads to a more accurate reliability model for majority voting based VLSI fault-tolerant circuits. The new model is extended to facilitate the calculation of reliability of fault-tolerant circuits which have sustained faults but continue to operate properly. Analysis of the reliability model indicates that, for some circuits, the reliability obtained with majority voting techniques is significantly greater than predicted by any previous model. >

Design of an efficient weighted random pattern generation system

Abstract: This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.

A 25-Ms/s 8-bit CMOS A/D converter for embedded application

Abstract: The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm/sup 2/ in a 1 /spl mu/m CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip. >

Architectural level test generation for microprocessors

Abstract: Hierarchically designed microprocessor-like VLSI circuits have complex data paths and embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely difficult. After the instruction sequence is derived, to assign values at all interior lines without conflicts is also very difficult. In this paper, we propose a separation of test generation process into two phases: path analysis and value analysis. In the phase of path analysis, a new methodology for automatic assembly of a sequence of instructions is proposed to satisfy the internal test goals. In the phase of value analysis, an equation-solving algorithm is used to compute an exact value solution for all interior lines. This new ATPG methodology containing techniques for both path and value analysis forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on six high-level circuits. The results show that our approach is very effective in achieving complete automation for high-level test generation. >

Analogue Neural Vlsi: A Pulse Stream Approach

Abstract: From the Publisher: Analogue VLSI is an important medium for the implementation of neural networks and the authors' aim in this book is to explore this technique in detail. This book compares a variety of approaches, giving readers an appreciation of analogue neural VLSI through examples of each approach rather than by means of an exhaustive survey.

Modern VLSI design

Abstract: From the Publisher: The state of the art in VLSI design: layouts, circuits, logic, floorplanning, and architectures New techniques for maximizing performance and minimizing power usage Extensive new coverage of advanced interconnect models, including copper Up-to-the-minute coverage of IP-based design Detailed HDL introductions: Verilog and VHDL The #1 VLSI design guide-now fully updated to reflect the latest advances in SoC design Modern VLSI Design, System-on-Chip Design, Third Edition is a comprehensive, "bottom-up" guide to the entire VLSI design process, focusing on the latest solutions for System-on-Chip (SoC) design. Wayne Wolf reviews every aspect of digital design, from planning and layout to fabrication and packaging, introducing today's most advanced techniques for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds. Coverage includes: Advanced interconnect models: new techniques for overcoming delay bottlenecks, reducing crosstalk, and modeling copper interconnect Advanced low-power design techniques for enhancing reliability and extending battery life in portable consumer electronics Testing solutions for every level of abstraction, from circuits to architecture Practical IP-based design solutions A thorough overview of HDLs, including new introductions to Verilog and VHDL Techniques for improving testability, embedded processors, and more VLSI design for today's high-performance, low-power devices requires broader, deeper skills than ever before. Modern VLSI Design, System-on-Chip, Third Edition brings together those skills in a single, comprehensive resource that will be invaluable to every VLSI design engineer and manager.