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Boon Teik Chan
Researcher at Katholieke Universiteit Leuven
Publications - 68
Citations - 688
Boon Teik Chan is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Layer (electronics) & Plasma etching. The author has an hindex of 13, co-authored 65 publications receiving 469 citations. Previous affiliations of Boon Teik Chan include Tokyo Electron.
Papers
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Journal ArticleDOI
A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$ -Based 1T1R CBRAM Cell
Attilio Belmonte,W. Kim,Boon Teik Chan,Nancy Heylen,Andrea Fantini,Michel Houssa,Malgorzata Jurczak,Ludovic Goux +7 more
TL;DR: The excellent Cu buffering properties of a TiW layer inserted at the Al-2O-3 interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400 °C and, on the other, to obtain excellent memory performances.
Journal ArticleDOI
Area-Selective Atomic Layer Deposition of TiN, TiO2, and HfO2 on Silicon Nitride with inhibition on Amorphous Carbon
Eric Stevens,Eric Stevens,Yoann Tomczak,Boon Teik Chan,Efrain Altamirano Sanchez,Gregory N. Parsons,Annelies Delabie +6 more
TL;DR: In this article, the initial growth of TiN, TiO2, and HfO2 thin films during thermal atomic layer deposition (ALD) onto a high density, amorphous carbon (aC) sacrificial layer was investigated.
Proceedings ArticleDOI
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
S. Subramanian,Maryamsadat Hosseini,Thomas Chiarella,S. Sarkar,P. Schuddinck,Boon Teik Chan,D. Radisic,G. Mannaert,Andriy Hikavyy,Erik Rosseel,Farid Sebaai,Antony Premkumar Peter,T. Hopf,P. Morin,S. Wang,Katia Devriendt,D. Batuk,G. T. Martinez,Anabela Veloso,E. Dentoni Litta,Sylvain Baudot,Yong Kong Siew,X. Zhou,B. Briggs,E. Capogreco,J. Hung,R. Koret,Alessio Spessot,Julien Ryckaert,Steven Demuynck,Naoto Horiguchi,Juergen Boemmels +31 more
TL;DR: This paper reports the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform and demonstrates functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices.
Journal ArticleDOI
Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow
Hari Pathangi,Boon Teik Chan,Hareen Bayana,Nadia Vandenbroeck,Dieter Van den Heuvel,Lieve Van Look,Paulina Rincon-Delgadillo,Yi Cao,Jihoon Kim,Guanyang Lin,Doni Parnell,Kathleen Nafus,Ryota Harukawa,Ito Chikashi,Marco Polli,Lucia D'Urzo,Roel Gronheid,Paul F. Nealey +17 more
TL;DR: In this article, the authors identify the issues and the level of control needed to achieve a stable DSA defect performance and identify the root causes of the DSA-induced defects and their kinetics of annihilation.
Proceedings ArticleDOI
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Anabela Veloso,Bertrand Parvais,Philippe Matagne,Eddy Simoen,T. Huynh-Bao,Vasile Paraschiv,E. Vecchio,Katia Devriendt,Erik Rosseel,M. Ercken,Boon Teik Chan,C. Delvaux,Efrain Altamirano-Sanchez,J. Versluijs,Z. Tao,Samuel Suhard,Stephan Brus,A. Sibaja-Hernandez,Niamh Waldron,P. Lagrain,O. Richard,Hugo Bender,Adrian Chasin,B. Kaczer,Tsvetan Ivanov,S. Ramesh,K. De Meyer,Julien Ryckaert,Nadine Collaert,Aaron Thean +29 more
TL;DR: In this article, the junctionless gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral configuration were compared to the conventional gate-and-allow mode (IM) GAA-NPNs, showing similar speed and voltage gain, and reduced LF noise.