J
J. Newbury
Researcher at IBM
Publications - 39
Citations - 2011
J. Newbury is an academic researcher from IBM. The author has contributed to research in topics: MOSFET & Gate dielectric. The author has an hindex of 19, co-authored 39 publications receiving 1936 citations.
Papers
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Proceedings ArticleDOI
High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling
Sarunya Bangsaruntip,Guy M. Cohen,Amlan Majumdar,Y. Zhang,Sebastian Engelmann,Nicholas C. M. Fuller,Lynne Gignac,S. Mittal,J. Newbury,Michael A. Guillorn,Tymon Barwicz,Lidija Sekaric,Martin M. Frank,Jeffrey W. Sleight +13 more
TL;DR: In this article, undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling were demonstrated.
Proceedings ArticleDOI
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
Kern Rim,Jack O. Chu,Huajie Chen,Keith A. Jenkins,Thomas S. Kanarsky,Kam-Leung Lee,Anda Mocuta,Huilong Zhu,Ronnen Andrew Roy,J. Newbury,John A. Ott,K. Petrarca,Patricia M. Mooney,D. Lacey,Steven J. Koester,Kevin K. Chan,Diane C. Boyd,Meikei Ieong,Hon-Sum Philip Wong +18 more
TL;DR: In this article, current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFets with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/ sub eff/ below 80 nm and 60 nm.
Proceedings ArticleDOI
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
J. Kedzierski,Edward J. Nowak,T. Kanarsky,Y. Zhang,Diane C. Boyd,Roy A. Carruthers,C. Cabral,R. Amos,Christian Lavoie,Ronnen Andrew Roy,J. Newbury,E. Sullivan,J. Benedict,P. Saunders,Keith Kwong Hon Wong,Donald F. Canaperi,Mahadevaiyer Krishnan,K.-L. Lee,Beth Ann Rainey,David M. Fried,Peter E. Cottrell,Hon-Sum P. Wong,Meikei Ieong,Wilfried Haensch +23 more
TL;DR: In this paper, metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation, and they satisfy the following metal gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on/I/sub off, and adjustable V/sub t/.
Proceedings ArticleDOI
High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices
J. Kedzierski,David M. Fried,Edward J. Nowak,Thomas S. Kanarsky,Jed H. Rankin,Hussein I. Hanafi,Wesley C. Natzle,Diane C. Boyd,Ying Zhang,Ronnen Andrew Roy,J. Newbury,Chienfan Yu,Qingyun Yang,P. Saunders,C.P. Willets,A.P. Johnson,S.P. Cole,H.E. Young,N. Carpenter,D. Rakowski,Beth Ann Rainey,Peter E. Cottrell,Meikei Ieong,Hon-Sum P. Wong +23 more
TL;DR: In this article, double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated and shown to have drain currents competitive with fully optimized bulk silicon technologies.
Patent
Interfacial oxidation process for high-k gate dielectric process integration
Arne W. Ballantine,Douglas A. Buchanan,Eduard A. Cartier,Kevin K. Chan,Matthew Copel,Christopher P. D'Emic,Evgeni Gousev,Fenton R. McFeely,J. Newbury,Harald F. Okorn-Schmidt,Patrick R. Varekamp,T. H. Zabel +11 more
TL;DR: In this paper, a method for integrating a high-k material into CMOS processing schemes is provided, which includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å.