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Yi-Chun Huang
Researcher at TSMC
Publications - 5
Citations - 176
Yi-Chun Huang is an academic researcher from TSMC. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 4, co-authored 5 publications receiving 170 citations.
Papers
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Proceedings ArticleDOI
High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme
C. C. Wu,Derek Lin,A. Keshavarzi,C.H. Huang,C.T. Chan,Tseng Chien-Hsien,Chun Chen,Hsieh Ching-Hua,King-Yuen Wong,M.L. Cheng,T.H. Li,Y.C. Lin,L.Y. Yang,C. P. Lin,Chuan-Ping Hou,H. C. Lin,J.L. Yang,K. F. Yu,Ming-Jer Chen,T.H. Hsieh,Y. C. Peng,Chou Chun-Hao,Lee Chia-Fu,Chien-Chao Huang,Chih-Yuan Lu,F.K. Yang,Huan-Neng Chen,L.W. Weng,P.C. Yen,Wang Shiang-Bau,Stock Chang,S.W. Chuang,T.C. Gan,Tzong-Lin Wu,Tsung-Lin Lee,W.S. Huang,Yi-Chun Huang,Y.W. Tseng,C.M. Wu,Eric Ou-Yang,K.Y. Hsu,L.T. Lin,S.B. Wang,Tsz-Mei Kwok,Chien-Chang Su,C.H. Tsai,Ming-Jie Huang,Huan-Just Lin,A.S. Chang,S.H. Liao,Li-Shiun Chen,J.H. Chen,P.S. Lim,X.F. Yu,S.Y. Ku,Yung-Huei Lee,P.C. Hsieh,Po-Kang Wang,Yuan-Hung Chiu,S.S. Lin,Hun-Jan Tao,M. Cao,Yuh-Jier Mii +62 more
TL;DR: In this article, a 22/20nm CMOS bulk FinFET with dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow.
Proceedings ArticleDOI
A 65nm node strained SOI technology with slim spacer
Fu-Liang Yang,Chien-Chao Huang,Hou-Yu Chen,Jhon-Jhy Liaw,Tang-Xuan Chung,Hung-Wei Chen,Chang-Yun Chang,Cheng Chuan Huang,Kuang-Hsin Chen,Di-Hong Lee,Hsun-Chih Tsao,Cheng-Kuo Wen,Shui-Ming Cheng,Yi-Ming Sheu,Ke-Wei Su,Chi-Chun Chen,Tze-Liang Lee,Shih-Chang Chen,C.H. Chen,Cheng-hung Chang,Jhi-cheng Lu,W. Chang,Chuan-Ping Hou,Ying-Ho Chen,Kuei-Shun Chen,Ming Lu,Li-Wei Kung,Yu-Jun Chou,Fu-Jye Liang,Jan-Wen You,King-Chang Shu,Bin-Chang Chang,Jaw-Jung Shin,Chun-Kuang Chen,Tsai-Sheng Gau,Bor-Wen Chan,Yi-Chun Huang,Han-Jan Tao,J.H. Chen,Yung-Shun Chen,Yee-Chia Yeo,Samuel Fung,Carlos H. Diaz,Chii-Ming Wu,Burn-Jeng Lin,Liang Min-Chang,J.Y.-C. Sun,Chenming Hu +47 more
TL;DR: In this article, a 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A/A//spl µ/m for N-FETs and P-Fet, respectively, at an off-state leakage of 40 nA/spl μ/m using 1 V operation.
Proceedings ArticleDOI
High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC
Yi-Chun Huang,C.-C. Lin,Jui-Cheng Huang,C. H. Hsieh,Chin-Hua Wen,Tung-Tsun Chen,L.-S. Jeng,C. K. Yang,Yang Jing-Hwang,Tsui Felix Ying-Kit,Yi-Shao Liu,Sheng-Da Liu,Ming-Jer Chen +12 more
TL;DR: A dual-gate ion-sensitive field effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented in this paper.
Patent
Spacer layer etch method providing enhanced microelectronic device performance
Hung Der Su,Hsu Ju-Wang,Yi-Chun Huang,Shien-Yang Wu,Yung-Shun Chen,Tung-Heng Shie,Yuan-Hung Chiu,J.H. Chen,Jhon Jhy Liaw +8 more
TL;DR: In this article, the gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and an anisotropic etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.
Patent
MOS transistor and fabrication method thereof
Su Hung-Der,Hsu Ju-Wang,Yi-Chun Huang,Shien-Yang Wu,Yung-Shun Chen,Shie Tung Heng,Chiu Yuan Hung,Chen Jyh Huei,Liaw Jhon Jhy +8 more
TL;DR: In this paper, a gate structure is provided for fabrication of MOS transistor, and the first and second spacers are then etched to expose a portion of the vertical sidewalls of the gate and adjacent to source/drain regions.