Yi-Chun Huang

TL;DR: In this article, a 22/20nm CMOS bulk FinFET with dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow.

TL;DR: In this article, a 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A/A//spl µ/m for N-FETs and P-Fet, respectively, at an off-state leakage of 40 nA/spl μ/m using 1 V operation.

TL;DR: A dual-gate ion-sensitive field effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented in this paper.

TL;DR: In this article, the gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and an anisotropic etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

TL;DR: In this paper, a gate structure is provided for fabrication of MOS transistor, and the first and second spacers are then etched to expose a portion of the vertical sidewalls of the gate and adjacent to source/drain regions.