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Yong-Hun Kim
Researcher at KAIST
Publications - 37
Citations - 257
Yong-Hun Kim is an academic researcher from KAIST. The author has contributed to research in topics: Jitter & Torque. The author has an hindex of 7, co-authored 34 publications receiving 141 citations. Previous affiliations of Yong-Hun Kim include Samsung.
Papers
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Journal ArticleDOI
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method
TL;DR: The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE, and the complexity and power consumption of the adaptation circuits are reduced significantly.
Journal ArticleDOI
Current and Position Sensor Fault Diagnosis Algorithm for PMSM Drives Based on Robust State Observer
TL;DR: The performance recovery property makes the proposed algorithm robust to parameter uncertainties and load variations, and sensitive only to sensor faults.
Proceedings ArticleDOI
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
Young-Ju Kim,Hye-Jung Kwon,Su-Yeon Doo,Yoon-Joo Eom,Young-Sik Kim,Min-Su Ahn,Yong-Hun Kim,Sang-Hoon Jung,Sung-Geun Do,Chang-Yong Lee,Jae-Sung Kim,Dong-seok Kang,Kyung-Bae Park,Jung-Bum Shin,Jong-Ho Lee,Seung-Hoon Oh,Sang-Yong Lee,Ji-Hak Yu,Ji-Suk Kwon,Ki-Hun Yu,Chul-Hee Jeon,Sang-Sun Kim,Min-Woo Won,Gun-hee Cho,Hyun-Soo Park,Hyung-Kyu Kim,Jeong-Woo Lee,Seung-Hyun Cho,Keon-woo Park,Jae-Koo Park,Lee Yong-Jae,Yong-Jun Kim,Young-Hun Seo,Beob-Rae Cho,Chang-Ho Shin,Chan-Yong Lee,Youngseok Lee,Yoon-Gue Song,Sam-Young Bang,Youn-sik Park,Seouk-Kyu Choi,Byeong-Cheol Kim,Gong-Heum Han,Seung-Jun Bae,Hyuk-Jun Kwon,Jung-Hwan Choi,Young-Soo Sohn,Kwang-Il Park,Seong-Jin Jang +48 more
TL;DR: This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.
Journal ArticleDOI
Energy-Shaping Speed Controller With Time-Varying Damping Injection for Permanent-Magnet Synchronous Motors
TL;DR: This brief presents a novel energy-shaping technique-based speed controller for permanent-magnet synchronous motors (PMSMs) considering machine nonlinearities and load and parameter changes and the result is provided to demonstrate its beneficial closed-loop properties.
Proceedings ArticleDOI
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM
Yong-Hun Kim,Hyung-Jin Kim,Jaemin Choi,Min-Su Ahn,Dongkeon Lee,Seung-Hyun Cho,Dong-Yeon Park,Young-Jae Park,Min-Soo Jang,Yong-Jun Kim,Jinyong Choi,Sung-Woo Yoon,Jae-Woo Jung,Jae-Koo Park,Jae-Woo Lee,Dae-Hyun Kwon,Hyung-Seok Cha,Si-Hyeong Cho,Seong-hoon Kim,Jihwa You,Kyoung-Ho Kim,Dae Hyun Kim,Byung-Cheol Kim,Young-Kwan Kim,Jun-Ho Kim,Seouk-Kyu Choi,Chan-Young Kim,Byongwook Na,Hye-In Choi,Reum Oh,Jeong-Don Ihm,Seung-Jun Bae,Nam Sung Kim,Jung-Bae Lee +33 more
TL;DR: In this article, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size, and the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier with dedicated Vthis articles for a 1-tap DFE.