Yong-Hun Kim

TL;DR: The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE, and the complexity and power consumption of the adaptation circuits are reduced significantly.

TL;DR: The performance recovery property makes the proposed algorithm robust to parameter uncertainties and load variations, and sensitive only to sensor faults.

TL;DR: This paper presents a 16Gb 18Gb/s/pin GDDR6 DRAM with a die architecture and high-speed circuit techniques on 1.35V DRAM process and introduces a dual channel for a data granularity of 32B with a BL16, per-bit training of l/REF, and an equalizer with PLL-less clocking.

TL;DR: This brief presents a novel energy-shaping technique-based speed controller for permanent-magnet synchronous motors (PMSMs) considering machine nonlinearities and load and parameter changes and the result is provided to demonstrate its beneficial closed-loop properties.

TL;DR: In this article, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size, and the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier with dedicated Vthis articles for a 1-tap DFE.