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Institution

Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.


Papers
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Patent
01 Aug 1994
TL;DR: In this paper, the authors proposed an antifuse structure capable of high density fabrication consisting of a first nitride/first amorphous silicon/second nitride under a plug of an electrically conductive material lined with titanium disposed between two metallization layers.
Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers, According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.

60 citations

Patent
18 Jul 1989
TL;DR: In this article, a method for programming an antifuse element which includes a pair of conductive electrodes separated by an insulating layer is presented, in which a predetermined number of voltage pulses are first applied across the electrodes of the Antifuse and the current drawn by the antifier is simultaneously measured.
Abstract: In a method for programming an antifuse element which includes a pair of conductive electrodes separated by an insulating layer a predetermined number of voltage pulses are first applied across the electrodes of the antifuse and the current drawn by the antifuse is simultaneously measured. When the measured current indicates that the antifuse dielectric has ruptured, a second step includes continuing to apply pulses and calculating the difference in current sensed between successive measurements. In a third step, a predetermined number of additional pulses are applied after the difference in current between successive pulses falls below a predetermined threshold. In a fourth step, an additional predetermined number of pulses are applied and the current drawn at the end of the sequence is measured. If it is greater than the current drawn at the beginning of the sequence by a predetermined threshold, the third step is repeated. If not, the programming process ends.

59 citations

Patent
17 Dec 1992
TL;DR: A metal-to-metal antifuse is a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure as discussed by the authors, and an upper electrode comprising a second metal layer including an underlying barrier layer is disposed over the second amorphous silicon layer.
Abstract: A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

57 citations

Patent
14 Apr 1995
TL;DR: In this paper, an antifuse is defined as a solid material consisting of first and second electrodes separated by an Antifuse material having a thickness selected to impart a desired target programming voltage to the antifuses.
Abstract: An antifuse comprises first and second electrodes separated by an antifuse material having a thickness selected to impart a desired target programming voltage to the antifuse. The antifuse material comprises a solid material stable at temperatures below about 600° C., having a defect density less than about 100 defects/cm2, a breakdown field less than about 10 megavolts/cm, a dielectric constant lower than about 4.0, a resistivity of greater than about 104 ohm-cm. The antifuse material may comprise organic materials such as polyimides compatible with high-temperature processes including cured polyamic acids, pre-imidazed polymers, photo-sensitive polyimides, and other polimides such as pyralin, probimide, PIQ, etc. The antifuse materials of the present invention also include fluorinated polymers having very low dielectric constants, such as teflon, paralines, polyphenylquinoxaline, benzocyclobutene polymers, and perfluoropolymers.

56 citations

Patent
17 May 1993
Abstract: A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output. A multiplexer is associated with each of the sequential logic elements, each of the multiplexers has a first input connected to one of the clock distribution lines, a second input connected to the output of the inverter, and a third input connected to a clock signal line connectable to at least one of the general interconnect line through a user-programmable element, an output connected to the clock input of the sequential element with which it is associated, and control inputs selecting which of the first, second, and third inputs is connected to the output.

56 citations


Authors

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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20151
20131
20124
20113
201019
200912