Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

Programming method for non-volatile memory and non-volatile memory-based programmable logic device

Abstract: A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

A technique for minimizing power during FPGA placement

Abstract: This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placement and is implemented in a commercial tool. In particular, a capacitance model based on multi-dimensional nonlinear regression is described, as well as a new capacitance model for global nets. The importance and advantages of these models are highlighted in terms of the overall attainable reduction in power in a real, commercially-available architecture and tool flow. The results are quantified across a range of industrial benchmarks targeting the Actelreg IGLOOtrade FPGA architecture. Power measurements show that, across a suite of 120 industrial designs, the technique described in this paper reduces dynamic power by 13% on average, with only a 1% degradation in timing performance.

Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication

Abstract: The present invention is directed to an antifuse structure and fabrication process wherein the bottom oxide of the ONO antifuse material layer is grown over a small area of N- diffusion surrounded by an N+ diffusion area where the N- diffusion could be patterned as N- "islands" or as N- "stripes", or the like, with the active N- area controlled by the formation and drive-in of the N+ diffusion layer. In this way, the bottom oxide layer of the ONO antifuse material layer is thinner at its center (above the N- region) than at its edges because oxide grows slower on the less doped N- region at the center of the antifuse than at the more heavily doped N+ regions at the edges of the antifuse. Forcing the center of the antifuse material layer to be thinner causes the antifuse to preferentially break down at its center and away from its edges. The opening in the antifuse cell opening mask is wider than the width of the N- diffusion area so that both N- and N+ areas are exposed in the antifuse cell opening step. Since the N+ diffusion can be very accurately dimensionally controlled with known techniques, it is thus possible to reduce the dimension of the active N- diffusion down to 0.2 μm or below, comparing favorably with the linear dimension of 1.0 μm used in currently available state-of-the-art manufacturing processes for antifuses. This represents a factor of 25 reduction in the active antifuse area, which in turn can dramatically reduce the defect density of antifuses over current technology and/or dramatically increase the number of antifuses that may be disposed in a given area of silicon.

Push-pull fpga cell

Abstract: A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.

Metal to metal antifuse

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed by means of collimated sputter deposition in the antifuse cell opening to form a layer of uniform thickness existing only within the antifuse cell opening in order to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer and optionally formed by collimated sputter deposition, and a top electrode disposed over the second barrier metal layer.