Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

Delay locked loop for an FPGA architecture

Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Metal-to-metal antifuses with very thin silicon dioxide films

Abstract: Antifuse samples with very thin insulating oxide were fabricated using a technique of two-step PECVD oxide deposition. Dielectric strength as high as 13 MV/cm was obtained for our samples. Defect density and uniformity have been improved in this way. The on-state resistance of the programmed antifuses shows a stronger dependence on the oxide thickness when it was programmed at the lower current than when it was programmed at the higher current. >

Methods for protecting outputs of low-voltage circuits from high programming voltages

Abstract: A method for isolating a first low-voltage circuit node comprising an output of a low-voltage device from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes the step of raising the normal power supply voltage provided to the low-voltage devices to an intermediate level lower than the programming voltage but high enough to protect the outputs of the low voltage devices from damage. The output to be protected is caused to assume a desired state and is then inhibited from changing state during the programming cycle. Programming voltage is then applied to the low voltage circuit node.

Testability circuits for logic arrays

Abstract: A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.

Conductive channel in ONO formed by controlled dielectric breakdown

Abstract: Cross-section TEM photos that capture the conductive channel of oxide-nitride-oxide (ONO) films after electric breakdown are discussed. The photos reveal a single crystal or polycrystal channel with a dome-shaped cap depending on the breakdown current. The implications of this structure for electric characteristics is analyzed with a spherical thermal-electric model. When ONO films are used as antifuse on FPGA product, the resistance of the antifuse can be controlled by choosing a sufficiently large programming current level and the resistance remains stable during 1000 h of burn-in at 125 degrees C and 5.75 V. Negligible change in delay time along many different data paths was observed. >