Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

Antifuse programmed PROM cell

Abstract: An antifuse based PROM cell design allows large currents to be sinked during cell programming to ensure low programmed resistance of the cell while using minimum-geometry select devices. This is achieved by utilizing a pseudo SCR latchup effect during programming. The regions in the semiconductor substrate (28a) forming lower antifuse electrodes for the antifuses in the PROM cells are doped at low levels with phosphorus. An antifuse layer (32a) formed from an oxide, oxide-nitride, or oxide-nitride-oxide antifuse layer, is formed over the lower antifuse electrode, and an upper antifuse electrode is formed from polysilicon. A minimum-geometry N-Channel select transistor is formed in series with the antifuse to complete the PROM cell. The drain (26a) and source (22a) diffusions of the select transistor are arsenic doped and the drain diffusion is contiguous with the lower antifuse electrode. A bit line (18a) is contacted to the upper antifuse electrode (34x) and the select transistor gate is part of a polysilicon word line. The source diffusion of the select transistor is grounded.

Field programmable gate array freeway architecture

Abstract: The disclosed system relates to a freeway routing system and a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises a two by two array of field programmable gate array tiles. Each tile comprises: a plurality of functional groups arranged in rows and columns; a plurality of interface groups surrounding the plurality of functional groups such that one interface group is positioned at each end of each row and column, each of the interface groups comprising a set of freeway input and output ports; a freeway set of routing conductors configured to transfer signals to the freeway input ports and from the output ports of the interface groups in each of the field programmable gate array tiles. The freeway set of routing conductors comprises: a plurality of vertical conductors that form intersections with a plurality of horizontal conductors; and programmable bi-directional three state interconnect elements located at the intersections. The fast-freeway routing system comprises: a first group of fast-freeway routing conductors, a second group of fast-freeway routing conductors, a third group of fast-freeway routing conductors, and a fourth group of fast-freeway routing conductors.

Inter-tile buffer system for a field programmable gate array

Abstract: An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.

Methods of reducing anti-fuse resistance during programming

Abstract: An already- programmed anti-fuse (10) is DC soaked by passing DC current through the anti-fuse from a DC voltage source applied across the electrodes (14,18) of the anti-fuse (10). The anti-fuse resistance is lower when the DC voltage being applied such that the positive end of the voltage source is applied to the electrode (14 or 18) having the higher arsenic concentration. An already programmed anti-fuse (10) is AC soaked, by passing alternating current pulses through the anti-fuse (10) from an AC voltage source applied across the anti-fuse electrodes (14,18). This AC soak may even be applied following the controlled polarity DC soak disclosed herein. The AC soaked anti-fuse resistance is even lower than the DC soaked anti-fuse resistance under the same soak current level.

Method of fabricating an antifuse element having an etch-stop dielectric layer

Abstract: A dielectric layer through which an antifuse via or an antifuse contact via is to be formed comprises a sandwich of at least two, and preferably three, individual layers. A first etch-stop dielectric layer is disposed over an underlying layer comprising either a lower or upper antifuse electrode barrier layer or an antifuse material layer. The first etch-stop dielectric layer comprises a thin layer of dielectric material. An isolation dielectric layer is disposed over the first etch-stop dielectric layer and comprises a second material comprising most of the thickness of the sandwich and having a substantial etch-time differential from the first etch-stop dielectric material for a selected etchant for the first etch-stop dielectric material. A second etch-stop dielectric layer may be provided under the first etch-stop dielectric layer and may be formed from a third material having a substantial etch time differential from the first etch-stop dielectric material for a selected etchant for the first material. A process for forming a via according to the present invention comprises, in order, the steps of forming the first etch-stop, isolation, masking the sandwich of dielectric layers for formation of a via; etching the isolation dielectric layer with an over-etch, stopping on the underlying first etch-stop dielectric layer; etching the first etch-stop dielectric layer with high over-etch, stopping on the layer beneath it.