Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

SRAM bus architecture and interconnect to an FPGA

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Antifuse structure comparison for field programmable gate arrays

Abstract: Antifuse structure as a programming element has become increasingly popular in field programmable gate array devices. In this paper we discuss the characteristics of various antifuse structures. Tradeoffs between performance and reliability are also discussed. >

Methods for preventing disturbance of antifuses during programming

Abstract: A method to minimize disturbance of an already programmed antifuse while programming other antifuses in a circuit includes the steps of determining a preferred order in which to program the antifuses and programming them in the preferred order. High initial programming and soak currents are selected such that the disturb current is small with respect thereto. The magnitude of the disturb current is increased to a value that maintains the antifuse resistance or improves it rather than adversely affect it. Where a circuit node containing a first already programmed antifuse is positioned such that parasitic capacitances may discharge through that antifuse during the programming of a second antifuse, the magnitude of the charge stored at parasitic capacitances associated with the programming path is reduced by reducing the programming voltage when this programming situation is detected. After the initial rupturing of the antifuse dielectric is detected, the programming voltage is increased to its normal value for the soaking period.

Accelerating FPGA routing using architecture-adaptive A* techniques

Abstract: The A* algorithm is a well-known path-finding technique that is used to speed up FPGA routing. Previously published A*-based techniques are either targeted to a class of architecturally similar devices, or require prohibitive amounts of memory to preserve architecture adaptability. This work presents architecture-adaptive A* techniques that require significantly less memory than previously published work. Our techniques are able to produce routing runtimes that are within 7% (on an island-style architecture) and 9% better (on a hierarchical architecture) than targeted heuristic techniques. Memory improvements range between 30/spl times/ (island-style) and 140/spl times/ (hierarchical architecture).

Distributed protocol framework

Abstract: A distributed computing system (6) having a distributed protocol stack (12). In a system including one or more general purpose computers or other application processors (8) for running applications (22), the distributed protocol stack (12) off-loads communication or other I/O processing from the application processor (8) to dedicated I/O processors (9) using a STREAMS environment thereby enhancing the performance/capacity of the system. The distributed protocol stack (12) is formed of a STREAMS stack top (15) and a stack bottom (16) so that together the stack top (15) and stack bottom (16) comprise a full stack (12) functionally equivalent to a non-distributed stack running on an application processor (8). Both the application processors (8) and the I/O processors (9) together appear to execute the full protocol stack (12), but the application processor (8) only executes the stack top (15) while the I/O processor only executes the stack bottom (16).