Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

Method of fabricating an antifuse

Abstract: An antifuse fabrication process includes the steps of forming a lower antifuse electrode, forming an insulating layer over the lower antifuse electrode, forming an antifuse aperture in the insulating layer, forming a dielectric antifuse material including a first layer comprising silicon dioxide and a second layer comprising silicon nitride over the antifuse insulating layer, etching the silicon nitride layer to form a small layer of silicon nitride in a region centered over the antifuse aperture, optionally forming a third dielectric antifuse layer comprising silicon dioxide, and forming an upper antifuse electrode. Alternatively, the first, second, and third layers of dielectric antifuse material may be formed and then etched to form a small composite sandwich structure of silicon nitride and silicon dioxide over the first silicon dioxide layer in a region centered over the antifuse aperture prior to forming an upper antifuse electrode.

Circuit and method for supplying programming potential at voltages larger than BVDss of programming transistors

Abstract: A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential V PP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of V PP /2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about V PP /2.

Floor plan for scalable multiple level interconnect architecture

Abstract: A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit. This floor plan is a scalable block architecture in which each block connector tab networks (410, 420, 430, 440, 450, 460, 470, 480) of a 2x2 block grouping (A, B, C) is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block (300) are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks (300) to share routing resources. In addition, this arrangement enables a 4x4 block grouping to be scalable.

An adaptive CMOS transmission line driver

Abstract: Fabrication process tolerances prevent the direct and precise matching of off-chip driver impedances to the impedances of driven transmission lines. The adaptive circuit described automatically adjusts the output impedance of a reference driver to that of a reference transmission line and generates a control voltage for adjusting the output impedances of the other drivers on the same chip to the same impedance. Simulation shows a ten-to-one reduction in the impedance mismatch. >

A hardware/software solution for embeddable FPGA

Abstract: This paper describes a novel FPGA architecture and related design software for embedding FPGA logic into ASIC designs. The requirements for embedding FPGAs include: fixed pinouts, predictable utilization, predictable and reasonable signal delays, scalability, die size control, and ease of layout. This paper describes Actel's embedded FPGA solution, VariCore/sup TM/.