Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

Low voltage programmable antifuse and method for programming same

Abstract: An antifuse structure according to a first aspect of the present invention is programmed by snap-back breakdown and includes a semiconductor substrate of a first conductivity type, an insulating layer over the surface of the semiconductor substrate, a conductive gate disposed over the insulating layer, spacer elements disposed at the outer edges of the conductive gate, spaced-apart first and second lightly doped regions of a second conductivity type disposed in the semiconductor substrate, the first and second lightly doped regions aligned to the edges of the conductive gate, third and fourth more heavily doped regions of the second conductivity type disposed in the semiconductor substrate, the third and fourth regions contiguous with the first and second regions, respectively, and aligned to the edges of the spacer elements, and a conductive filament in the insulating layer connecting the conductive gate to one of the second and fourth doped regions. An antifuse element according to a second aspect of the present invention is programmed by gate-aided breakdown and includes a semiconductor substrate of a first conductivity type, an insulating layer over the surface of the semiconductor substrate, a conductive gate disposed over the insulating layer, a spacer element disposed at a selected outer edge of the conductive gate, a lightly doped region of a second conductivity type disposed in the semiconductor substrate aligned to the selected outer edge of the conductive gate, a more heavily doped region of the second conductivity type disposed in the semiconductor substrate aligned to the edge of the spacer element, and a conductive filament in the insulating layer connecting the conductive gate to one of the doped region.

Fast and accurate delay estimation for use in timing driven layout for FPGAs with segmented channels

Abstract: Timing delays for FPGAs with segmented channels can be accurately estimated by most SPICE-like circuit simulators. Such simulators however, are too slow to be of any use inside an iterative automatic timing driven layout (ATDL) engine, which may repeat the computations millions of times. Other methods such as half-perimeter approximation are very easy and fast to compute, but accuracy is very poor for these kinds of FPGAs. The method published by Chew and Lien [1994] overcomes these problems; however, it introduces a very large number of fitted parameters, and its accuracy decreases for more complicated topologies. We present a method similar to Chew and Lien's, but with better accuracy and far fewer coefficients. This is achieved by taking advantage of the symmetry of the problem under the permutation group S/sub N/ of N objects.

Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof

Abstract: An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the first high-voltage inverter and a second low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the other high-voltage inverter. The gate of the first low-voltage n-channel MOS transistor is coupled to one output of one of the inverters forming the assembly buffer latch and the gate of the second low-voltage n-channel MOS transistor is coupled to the output of the other one of the inverters forming the assembly buffer latch. A pre-load circuit is used to prevent data in an unselected circuit from being disturbed.

Enhanced filed programmable gate array

Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

Cad for Field Programmable Gate Arrays

Abstract: The sections in this article are 1 Technology Mapping 2 Partitioning 3 Placement 4 Routing 5 Commercial CAD Software 6 Future Trends in FPGA CAD Research and Development