Actel

About: Actel is a based out in . It is known for research contribution in the topics: Antifuse & Field-programmable gate array. The organization has 364 authors who have published 402 publications receiving 12674 citations.

Power-up and power-down circuit for system-on-a-chip integrated circuit

Abstract: A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.

Split instruction and operand cache management

Abstract: of EP0271187A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic managment of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

Design and Layout Effects on SET Propagation in 90-nm ASIC and FPGA Test Structures

Abstract: SET propagations in ASIC-like and FPGA-like digital circuits are investigated, using 90-nm test structures, by fault injection and radiation tests. SET fault injection tests are used to show the dependence of the final SET-pulse on the design and layout of the logic circuit.

Antifuses having minimum areas

Abstract: Antifuses having minimum areas are formed by a process including the steps of forming doped regions (12) in a semiconductor substrate, forming a dielectric layer (14,16) over the surface of the substrate, performing masking and etching steps to form apertures in the dielectric layer over portions of the doped regions where antifuses are to be formed, depositing a second dielectric layer (20) over the first dielectric layer and the apertures, the second dielectric layer having a faster etch rate than the first dielectric layer, etching the second dielectric layer to leave spacers (22) at the edges of the apertures, forming the antifuse dielectric (26) in the apertures, and forming upper antifuse electrodes (28) over the antifuse dielectric. In another process, a process for forming antifuses includes the steps of forming a dielectric layer over the surface of a semiconductor substrate, forming a first layer of polysilicon over the insulating layer, forming apertures in between portions of the first polysilicon layer where antifuses are to be formed, doping the exposed regions in the substrate using the polysilicon as a masking member, depositing an oxide over the polysilicon regions, etching the oxide to expose the substrate between the regions of first layer polysilicon, forming the antifuse dielectric in the apertures, and forming upper antifuse electrodes over the antifuse dielectric. The process of the present invention may also be used to form antifuses in layers above the substrate.