Showing papers by "Freescale Semiconductor published in 2014"

A Review of High-Frequency Power Distribution Systems: For Space, Telecommunication, and Computer Applications

Abstract: High-frequency AC (HFAC) power distribution systems have been the subject of great interest over the last several decades. This paper presents a thorough review of different HFAC power distribution architectures on which the authors have worked in the last 30 years. The review is focused on the HFAC power architectures and topologies for space, telecommunications, and computer applications. Detail of each architecture is given and evaluated in terms of performance specific to each application.

Impact of Technology Scaling on SRAM Soft Error Rates

Abstract: Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

Wireless charging systems, devices, and methods

Abstract: A wireless charging system (100, 200) includes a power transmitting device (110, 210) and a power receiving device (130, 230). In the transmitting device, a transmitting coil (212) converts (302) a drive signal from a drive signal circuit (216) into an alternating magnetic field. In the receiving device, a receiving coil (232) produces (402) an alternating waveform from the magnetic field, and a rectifier (234) rectifies (404) the alternating waveform to deliver power having a rectified voltage. A modulation circuit (248) causes (408) a loading circuit (260) to be coupled to and uncoupled from the receiving coil at a pre-determined modulation rate when, for example, the rectified voltage is greater than a threshold voltage. Back in the transmitting device, a modulation detector circuit (218) detects (304, 306) modulation of the load impedance, and when the load impedance is modulating at the pre-determined modulation rate, causes (310) the drive signal circuit (216) to adjust a characteristic of the drive signal, resulting in an adjustment in an intensity of the magnetic field.

Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection

Abstract: This paper presents the Quick Error Detection (QED) technique for systematically creating families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory controllers, and on-chip interconnection networks) of multicore system on chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of traditional post-silicon validation approaches. QED can be implemented completely in software, without any hardware modification. Hence, it is readily applicable to existing designs. Results using multiple hardware platforms, including the Intel® Core™ i7 SoC, and a state-of-the-art commercial multicore SoC, along with simulation results using an OpenSPARC T2-like multicore SoC with bug scenarios from commercial multicore SoCs demonstrate: 1) error detection latencies of post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs inside uncore components; 2) QED shortens error detection latencies by up to nine orders of magnitude to only a few hundred cycles for most bug scenarios; and 3) QED enables up to a fourfold increase in bug coverage.

Memory Redundancy to Replace Addresses with Multiple Errors

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory ( 18 ), second memory ( 14 ), and redundant memory ( 19 ) to perform error correction code (ECC) processing on data retrieved from the first memory ( 18 ) by using the redundant memory ( 19 ) to replace entries in the second memory ( 14 ) having repeat addresses, thereby freeing entries in the second memory ( 14 ) for use in detecting and managing errors identified by the ECC processing.

Resistive memory with program verify and erase verify capability

Abstract: A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing, during the applying the programming voltage, determines if the resistive non-volatile memory cell has been programmed. Current is limited through the resistive non-volatile memory cell to a first magnitude. After a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, the current through the resistive non-volatile memory cell is limited to a second magnitude greater than the first magnitude. The resistive non-volatile memory cell is also erased.

Universality of NBTI - From devices to circuits and products

Abstract: This paper showcases the universality of NBTI and its dependencies on time, bias, temperature, AC frequency and pulse duty cycle across different process integration schemes used in the industry and technology nodes. Strong correlation has been established between device, circuit, and product degradation. Different aspects of variability and variable NBTI in small area devices have been discussed. Features that are important from an industrial perspective are highlighted. Any NBTI model should address these aspects to be considered relevant.

Geometry Dependence of Total-Dose Effects in Bulk FinFETs

Abstract: The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and fin pitch. The buildup of oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher IOFF.) The TID-induced degradation increases with decreasing fin width. Transistors with longer channels degrade less than those with shorter channels. Transistors with large fin pitch degrade more, compared to those with narrow fin pitch. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current. The strong influence of charge in the STI in narrow-fin transistors induces a parasitic leakage current path between the source and the drain, while in wide-fin devices, for the same amount of trapped charge in the isolation oxide, the subsurface leakage path is less effective.

A 350 W, 790 to 960 MHz wideband LDMOS doherty amplifier using a modified combining scheme

Abstract: A modified Doherty combining scheme is proposed that eases the impedance matching requirement and enables excellent AM/AM, AM/PM, and wide bandwidth in practical designs A 350 W, 790 to 960 MHz symmetrical LDMOS Doherty amplifier measured 20 to 21 dB gain as well as peak and back-off efficiencies of 56% to 61% and 48% to 50% respectively across the band The amplifier achieved excellent linearization results when driven with wideband 20 and 50 MHz WCDMA signals and a 35 MHz GMSK signal

Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

Abstract: This paper presents a methodology dedicated to modeling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz.

Software Defined Networking: Redefining the Future of Internet in IoT and Cloud Era

Abstract: Ubiquitous computing with smart mobile devices, Internet of Things, virtualization and cloud is changing yesteryears' static networks to dynamic networks of mobile smart devices and cloud based on-demand services. These changes are growing exponentially and network management is becoming increasingly difficult, be it in smart energy/ transport/cities or in big enterprises. The diverse nature of applications, devices, mobility of the endpoints has challenged IT to look beyond conventional applications for effective security policies, quality of service and performance. This paper describes how the emerging technology- Software Defined Networking (SDN) can be leveraged to provide scalable solutions in this diverse and rapidly changing landscape, reducing both capex and opex. Two use cases, SDN enabled IoT gateways and eNodeB, are covered in this paper. These use cases demonstrate how SDN can be effectively used to address the challenges faced by service providers/IT in managing the dynamic nature of today's networks. These solutions and other such services with help of North Bound APIs can be used in areas like wireless networks, data centers, service providers, enterprise gateways and other such deployments where there is a need to dynamically program networks to make them agile, smarter and faster.

Modified field oriented control for smooth torque operation of a BLDC motor

Abstract: This paper describes a novel approach to field oriented control of a BLDC (Brushless Direct-Current) motor producing a significantly reduced torque ripple. This paper presents a standard mathematical model of a BLDC motor in the abc reference frame which is suitable for simulation of the six-step control strategy, and a mathematical model of a BLDC motor in the dq reference frame suitable for standard and modified field oriented control strategies. An extended dq transformation, in other words a Park's-like transformation, is described and implemented in the simulation model. Simulation results of all the control strategies are evaluated and compared.

RF power transistor circuits

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

SVA: The Power of Assertions in SystemVerilog

Abstract: This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

Semiconductor device and related fabrication methods

Abstract: Semiconductor device structures and related fabrication methods are provided An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region

High strain rate mechanical properties of SAC105 leadfree alloy at high operating temperatures

Abstract: Industry migration to leadfree solders has resulted in a proliferation of a wide variety of solder alloy compositions. The most popular amongst these are the Sn-Ag-Cu family of alloys like SAC105 and SAC305. Electronics subjected to shock and vibration may experience strain rates of 1-100 per sec. Electronic product may often be exposed to high temperature during storage, operation and handling in addition to high strain rate transient dynamic loads during drop-impact, shock and vibration. Properties of leadfree solder alloys at high strain rates at low and high temperatures experienced by the solder joint during typical mechanical shock events are scarce. Previous studies have showed the effect of high strain rates and thermal aging on the mechanical properties of leadfree alloys including elastic modulus and the ultimate tensile strength. The ANAND viscoplastic constitutive model has been widely used to describe the inelastic deformation behavior of solders in electronic components. In this study, SAC105 leadfree alloys have been tested at strain rates of 10, 35, 50 and 75 per sec at various operating temperatures of 50°C, 75°C, 100°C and 125°C. Full-field strain in the specimen have been measured using high speed imaging at frame rates up to 75,000 fps in combination with digital image correlation. The cross-head velocity has been measured prior-to, during, and after deformation to ensure the constancy of cross-head velocity. Stress-Strain curves have been plotted over a wide range of strain rates and temperatures. Experimental data for the pristine specimen has been fit to the ANAND's viscoplastic model.

Shielded device packages having antennas and related fabrication methods

Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.

Yield optimization using advanced statistical correlation methods

Abstract: This work presents a novel yield optimization methodology based on establishing a strong correlation between a group of fails and an adjustable process parameter. The core of the methodology comprises three advanced statistical correlation methods. The first method performs multivariate correlation analysis to uncover linear correlation relationships between groups of fails and measurements of a process parameter. The second method partitions a dataset into multiple subsets and tries to maximize the average of the correlations each calculated based on one subset. The third method performs statistical independence test to evaluate the risk of adjusting a process parameter. The methodology was applied to an automotive product line to improve yield. Five process parameter changes were discovered which led to significant improvement of the yield and consequently significant reduction of the yield fluctuation.

Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof

Abstract: Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.

3d device packaging using through-substrate posts

Abstract: A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a third surface and a set of metal posts. The first die and the second die are stacked such that the third surface of the second die faces the second surface of the first die, and each metal post extends through a corresponding through-hole to a point beyond the first surface of the first die, electrically coupling the first die and the second die.

Microelectronic packages having sidewall-deposited heat spreader structures and methods for the fabrication thereof

Abstract: Microelectronic packages and methods for producing microelectronic packages having sidewall-deposited heat spreader structures are provided. In one embodiment, the method includes providing a package body containing a microelectronic device. A heat spreader structure is printed or otherwise formed over at least one sidewall of the package body. The heat spreader structure is thermally coupled to the microelectronic device and is configured to dissipate heat generated thereby during operation of the microelectronic package.

Non-volatile memory using bi-directional resistive elements

Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

Abstract: To meet the electrical performance requirements, copper traces with ultralow- k (ULK) interlayer dielectric (ILD) materials are used in today's semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model,” which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.

Stacked die package with redistribution layer

Abstract: A packaged semiconductor device has lead fingers that define a cavity, and a first die located within the cavity. A second die abuts an inactive side of the first die. The second die is electrically connected to one or more of the lead fingers. A redistribution layer abuts an active side of the first die. Metal structures are situated on an outer surface of the redistribution layer. The redistribution layer electrically connects (i) one or more of the metal structures to one or more of the lead fingers and (ii) one or more of the metal structures to one or more bond pads on the active side of the first die.

Modifiable signal adjustment devices for power amplifiers and corresponding methods & apparatus

Abstract: An embodiment of an amplifier system includes a modifiable signal adjustment device with an RF signal adjustment circuit coupled between first and second nodes. The RF signal adjustment circuit includes an adjustable phase shifter and an adjustable attenuator coupled in series with each other. The device also includes a memory and a controller circuit. The controller circuit retrieves a phase shift value and an attenuation value from the memory. The controller circuit then controls the adjustable phase shifter to apply a phase shift corresponding to the phase shift value to an input RF signal received at the first node, and controls the adjustable attenuator to apply an attenuation corresponding to the attenuation value to the input RF signal. Applying the phase shift and the attenuation results in an output RF signal at the second node.

Copper versus palladium coated copper wire process and reliability differences

Abstract: Fine pitch copper wire bonding presents challenges to both first and second bond processes. Corrosion of the first bond copper-aluminum (Cu-Al) intermetallic compound bond interface layer can be induced by mobile chlorine in the epoxy mold compound, and the second bond process window can be narrower than with gold wire. Palladium-coated copper wire is believed to overcome these two problems, however, the actual benefits and challenges of the wire need to be considered by the semiconductor industry. The price of palladium-coated copper wire is 2.5-3 times higher than bare copper wire. The mechanical properties of palladium-coated copper wire increase the risk of damaging bond pad structures if not bonded correctly. The addition of a thin palladium layer can increase electrical resistivity, which can be a concern for high frequencies and smaller diameter wire applications. Others promote palladium-coated copper wire with reports of improved biased highly accelerated stress test (HAST) results versus bare copper wire. As a consequence, debate over the choice between palladium-coated and bare copper wire is common. Some semiconductor suppliers and original equipment manufacturers (OEMs) incorrectly believe that palladium-coated copper wire is a panacea for all historical concerns with the use of bare copper wire. A study has been conducted to assess advantages and disadvantages of bare and palladium-coated copper. This paper shows bare copper wire can provide the same level of chlorine-induced corrosion resistance as palladium-coated copper wire if the copper-aluminum intermetallic bond is properly formed and the mold compound is correctly formulated. The basis for the belief that palladium-coated copper wire provides better resistance to chlorine-induced corrosion is explained and the electrical performance difference between palladium-coated and bare copper wires is discussed. High temperature (175°C) storage life testing, up to 7000 hours, was conducted with both wire types to determine the end-of-life failure mechanism. Bond interface cracking, initiating in the bond periphery, was observed. The time dependence of copper-aluminum intermetallic phase transformation for both wire types will be presented. It is shown that choice criteria for each wire type can be defined by product field application requirements and not by perceived advantages. The reported work shows bare copper has equal performance to palladium-coated copper wire under Automotive Electronic Council (AEC) reliability grade 1 in specified package types when the bonding process, substrate / lead frame design and mold compound have been correctly optimized [1].

Explicit barrier scheduling mechanism for pipelining of stream processing algorithms

Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.

Microelectronic packages having mold-embedded traces and methods for the production thereof

Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.