International Rectifier

About: International Rectifier is a company organization based out in Wrexham, Wales [Cymru GB-CYM], United Kingdom. It is known for research contribution in the topics: Power semiconductor device & Transistor. The organization has 767 authors who have published 1624 publications receiving 27118 citations.

Superjunction device with self compensated trench walls

Abstract: A superjunction device has a large number of symmetrically located vertical circular wells in a high resistivity silicon substrate. A plurality of alternate opposite conductivity N and P stripes or nodes are formed along the length of the walls of each of the wells. Each of the nodes faces an opposite concentration type node in an adjacent well. A DMOS gate structure is connected to the tops of the N stripes. The nodes have a depth and concentration to cause full depletion of all nodes during reverse bias. Current flows through the relatively low resistance N stripes when its gate is turned on. A conventional termination such as a diffused ring or rings can surround the active area of all cells and is formed in the high resistivity substrate.

Three commonly housed diverse semiconductor dice

Abstract: An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Reset dominant level-shift circuit for noise immunity

Abstract: The logic circuit of the level shifting circuit of a high side MOS gate device is made reset dominant to make the circuit immune to noise glitches. The reset dominance is obtained by causing a reset signal to be produced at a wider range of high side floating supply offset voltage than that at which the set signal can be produced to prevent the chance of a set when the high side power MOSFET should be off. The reset dominance is obtained by increasing the size of the reset voltage dropping resistor or by adjusting the input threshold of the circuit reading the set and reset voltage dropping resistors.

Commonly housed diverse semiconductor die with reduced inductance

Abstract: A MOSFET die and a Schottky diode die are each mounted within a device package on a common lead frame pad with their drain and cathode terminals, respectively, connected together at the common pad The source terminal of the MOS gated device and the anode terminal of the Schottky diode are each electrically connected by wire bonds to an insulated pin, and the gate electrode of the MOS gated device is electrically connected by wire bonds to another pin A redundant wire connection runs from the source terminal of the MOS gated device to the anode terminal of the Schottky diode reduce the inductance in the anode lead

Power MOSFET with overcurrent and over-temperature protection

Abstract: A power integrated circuit is pin-compatible with a three-terminal power MOSFET and contains integrated circuits to turn off the device in the event of an overcurrent or an over-temperature condition. Control power voltage V cc is applied through a first MOSFET connected between the gate pin and the gate electrode of the power device. A second control MOSFET is connected across the power device gate and source electrodes. The first control MOSFET is turned off and the second control MOSFET is turned on in response to a fault condition. The turn off of the first MOSFET limits the current sinked by the gate pin. A novel boot strap circuit is disclosed which permits the use of all N channel MOSFETs with an N channel power device, and a novel trimmable temperature shutdown circuit is provided. An integrated bipolar transistor is also integrated into the chip to prevent conduction of the P well/N epi diode formed in the device substrate.