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Institution

International Rectifier

CompanyWrexham, Wales [Cymru GB-CYM], United Kingdom
About: International Rectifier is a company organization based out in Wrexham, Wales [Cymru GB-CYM], United Kingdom. It is known for research contribution in the topics: Power semiconductor device & Transistor. The organization has 767 authors who have published 1624 publications receiving 27118 citations.


Papers
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Patent
02 Aug 2013
TL;DR: In this paper, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III -V transistor, and a driver IC in group IV die.
Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.

20 citations

Patent
04 Mar 2005
TL;DR: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device, is defined in this article.
Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

20 citations

Patent
06 Jan 2003
TL;DR: In this paper, a high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a V s node to ground to discharge the load capacitance.
Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a V s node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

20 citations

Patent
20 Dec 2004
TL;DR: In this paper, a control terminal driver circuit for a switching amplifier including a driver (66, 69) for each of a pair of output power transistors (56, 58) responsive to a PWM information signal is presented.
Abstract: A control terminal driver circuit for a switching amplifier including a driver (66, 69) for each of a pair of output power transistors (56, 58) responsive to a PWM information signal. The circuit operates in response to an operating state signal (91) indicating a start up condition of the amplifier to vary the amplitude of the drive pulses for the output transistors (56, 58) between a zero value and a maximum value for normal operation of the amplifier over a start up interval, and to reverse the process during a shut down interval. A DC offset detector (74) is provided to detect a DC offset at amplifier output, and an error circuit (86) responsive to an output of the DC offset detector (74) controls the relative amplitude of the driver outputs during at least a portion of the start up interval to substantially eliminate the DC offset. Also disclosed is a switching amplifier including a control terminal driver circuit as described above.

20 citations

Patent
09 Feb 1998
TL;DR: In this article, a MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.
Abstract: A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.

20 citations


Authors

Showing all 768 results

NameH-indexPapersCitations
Robert S. Brown130124365822
Praveen Jain5962711528
Edwin L. Piner421625020
Jerry W. Johnson371093522
Steffen Rupp361574848
Kevin J. Linthicum361174334
Andrei Vescan312073308
Thomas Gehrke28812753
Pradeep Rajagopal27652282
Thomas J. Ribarich24831547
Daniel M. Kinzer23822054
Bo Yang21403331
Johan Strydom21752159
Michael A. Briere191421200
Robert Joseph Therrien19561441
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20221
20201
20192
20183
20175
201611