Institution
International Rectifier
Company•Wrexham, Wales [Cymru GB-CYM], United Kingdom•
About: International Rectifier is a company organization based out in Wrexham, Wales [Cymru GB-CYM], United Kingdom. It is known for research contribution in the topics: Power semiconductor device & Transistor. The organization has 767 authors who have published 1624 publications receiving 27118 citations.
Papers published on a yearly basis
Papers
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02 Aug 2013TL;DR: In this paper, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III -V transistor, and a driver IC in group IV die.
Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.
20 citations
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04 Mar 2005TL;DR: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device, is defined in this article.
Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.
20 citations
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06 Jan 2003TL;DR: In this paper, a high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a V s node to ground to discharge the load capacitance.
Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a V s node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.
20 citations
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20 Dec 2004TL;DR: In this paper, a control terminal driver circuit for a switching amplifier including a driver (66, 69) for each of a pair of output power transistors (56, 58) responsive to a PWM information signal is presented.
Abstract: A control terminal driver circuit for a switching amplifier including a driver (66, 69) for each of a pair of output power transistors (56, 58) responsive to a PWM information signal. The circuit operates in response to an operating state signal (91) indicating a start up condition of the amplifier to vary the amplitude of the drive pulses for the output transistors (56, 58) between a zero value and a maximum value for normal operation of the amplifier over a start up interval, and to reverse the process during a shut down interval. A DC offset detector (74) is provided to detect a DC offset at amplifier output, and an error circuit (86) responsive to an output of the DC offset detector (74) controls the relative amplitude of the driver outputs during at least a portion of the start up interval to substantially eliminate the DC offset. Also disclosed is a switching amplifier including a control terminal driver circuit as described above.
20 citations
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09 Feb 1998TL;DR: In this article, a MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.
Abstract: A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel regions to form respective source regions therein. The periphery of each of the source regions is spaced from the periphery of its respective channel region at the surface to define N-type channel regions between the spaced peripheries. A layer of gate oxide is formed over the channel areas. A doped polysilicon gate electrode is formed atop the gate oxide. A source electrode is formed atop the source regions. The MOS gated device is optimized to maintain a threshold voltage of between -2V to -5V for a total irradiation dose of 300 Krad while maintaining SEE withstand capability.
20 citations
Authors
Showing all 768 results
Name | H-index | Papers | Citations |
---|---|---|---|
Robert S. Brown | 130 | 1243 | 65822 |
Praveen Jain | 59 | 627 | 11528 |
Edwin L. Piner | 42 | 162 | 5020 |
Jerry W. Johnson | 37 | 109 | 3522 |
Steffen Rupp | 36 | 157 | 4848 |
Kevin J. Linthicum | 36 | 117 | 4334 |
Andrei Vescan | 31 | 207 | 3308 |
Thomas Gehrke | 28 | 81 | 2753 |
Pradeep Rajagopal | 27 | 65 | 2282 |
Thomas J. Ribarich | 24 | 83 | 1547 |
Daniel M. Kinzer | 23 | 82 | 2054 |
Bo Yang | 21 | 40 | 3331 |
Johan Strydom | 21 | 75 | 2159 |
Michael A. Briere | 19 | 142 | 1200 |
Robert Joseph Therrien | 19 | 56 | 1441 |