Proceedings ArticleDOI
3D VLSI: A Scalable Integration Beyond 2D
Karim Arabi,Kambiz Samadi,Yang Du +2 more
- pp 1-7
TLDR
3D VLSI (3DV) is an emerging 3D integration technology that unlike packaging-driven 3D technologies can deliver orders of magnitude more integration densities due to extremely small sizes of vertical vias.Abstract:
As the semiconductor industry faces serious challenges extending the CMOS roadmap, traditional cost reduction benefits that accompanied power/performance/area (PPA) advantages of successive technology nodes have decreased due to a myriad of process integration challenges and increased variability, reliability, power and thermal constraints. 3D integration technologies have been pursued as a potential solution to help integrate more functions within a confined available dimensions of advanced mobile devices. 3D VLSI (3DV) is an emerging 3D integration technology that unlike packaging-driven 3D technologies (e.g., 2.5D, TSV-based 3D, etc.) can deliver orders of magnitude more integration densities due to extremely small sizes of vertical vias. In this paper, we describe the 3DV technology and its current benefits and challenges. We also survey recent literature that show the potential of 3DV to help continue Moore's law trajectory beyond 2D.read more
Citations
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Journal ArticleDOI
Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits
TL;DR: The results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm, and test-generation methods must be enhanced to take M3d fabrication defects into account.
Proceedings ArticleDOI
Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper)
TL;DR: In this article, the authors provide a survey of work that addresses the power, performance, area, and reliability (PPAR) advantages of M3D over TSV, but they also point out some drawbacks, such as device and interconnect performance mismatch between tiers, lack of EDA solutions, testing challenges, and cost.
Proceedings ArticleDOI
Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing
TL;DR: The results show that significant rethinking in test generation is needed to effectively screen delay defects in M3D ICs and the impact of coupling on the effectiveness of delay-test patterns using the statistical delay quality level (SDQL) as a metric.
Journal ArticleDOI
A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits
TL;DR: This work proposes a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers, and presents a test scheduling and optimization technique for wafer-level testing of M3d ICs.
Journal ArticleDOI
Towards Reconfigurable Electronics: Silicidation of Top-Down Fabricated Silicon Nanowires
Muhammad Bilal Khan,Dipjyoti Deb,Jochen Kerbusch,Florian Fuchs,Markus Löffler,Sayanti Banerjee,Uwe Mühle,Walter M. Weber,Sibylle Gemming,Jörg Schuster,Artur Erbe,Yordan M. Georgiev +11 more
TL;DR: In this paper, the effects of variations in crystallographic orientations of SiNWs and different NW designs on the silicidation process are studied, and the effect of Ni diffusion, silicide phases, and silicide-silicon interfaces are investigated.
References
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Proceedings ArticleDOI
Advances in 3D CMOS sequential integration
Perrine Batude,Maud Vinet,A. Pouydebasque,C. Le Royer,Bernard Previtali,Claude Tabone,J.M. Hartmann,Loic Sanchez,L. Baud,V. Carron,Alain Toffoli,F. Allain,V. Mazzocchi,D. Lafond,Olivier P. Thomas,O. Cueto,N. Bouzaida,D. Fleury,Amara Amara,Simon Deleonibus,O. Faynot +20 more
TL;DR: In this article, a 3D sequential CMOS integration of top Si active layers is presented, and the electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm.
Proceedings ArticleDOI
Design and CAD methodologies for low power gate-level monolithic 3D ICs
TL;DR: This paper develops, for the first time, a complete RTL-to-GDSII design flow for gate-level M3D, and uses this flow along with a 28nm PDK to build layouts for the OpenSPARC T2 core.
Proceedings ArticleDOI
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations
TL;DR: This study shows that it can close the power-performance gap between 2D and a theoretical lower bound by up to 50% and proposes a variation-aware floorplanning technique that makes the design more tolerant to these variations.
Journal ArticleDOI
Scaling: More than Moore's law
TL;DR: This column examines the ITRS definitions associated with "More than Moore", along with their implications, and examines the implications of these definitions for IC design and test.
Proceedings ArticleDOI
New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI
Claire Fenouillet-Beranger,B. Mathieu,Bernard Previtali,M.-P. Samson,N. Rambal,V. Benevent,Sebastien Kerdiles,J.P. Barnes,D. Barge,Pascal Besson,R. Kachtouli,M. Casse,X. Garros,A. Laurent,Fabrice Nemouchi,Karim Huet,I. Toque-Tresonne,D. Lafond,H. Dansas,F. Aussenac,G. Druais,Pierre Perreau,E. Richard,S. Chhun,E. Petitprez,N. Guillot,F. Deprat,L. Pasini,Laurent Brunet,V. Lu,C. Reita,Perrine Batude,M. Vinet +32 more
TL;DR: In this article, the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in sequential 3D integration.
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