Journal ArticleDOI
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation
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TLDR
In this article, a digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs.Abstract:
A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm2.read more
Citations
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Journal ArticleDOI
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power
Davide Tasca,Marco Zanuso,Giovanni Marzin,Salvatore Levantino,Carlo Samori,Andrea L. Lacaita +5 more
TL;DR: This paper introduces a fractional-N PLL based on a 1b TDC, achieving jitter of 560fsrms (from 3kHz to 30MHz) at 4.5mW power consumption, even in the worst-case of fractional spur falling within the PLL bandwidth.
Journal ArticleDOI
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
TL;DR: The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution and is less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL.
Journal ArticleDOI
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
TL;DR: This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in- band phase noise of -103 dBc/Hz and power consumption of 4.2 mW.
Journal ArticleDOI
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps
TL;DR: Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation.
Journal ArticleDOI
A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
TL;DR: This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-Slope method.
References
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Journal ArticleDOI
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS
Robert Bogdan Staszewski,Khurram Muhammad,Dirk Leipold,Chih-Ming Hung,Yo-Chuol Ho,John Wallberg,C. Fernando,Ken Maggio,Roman Staszewski,T. Jung,Jinseok Koh,S. John,I. Deng,Vivek Sarda,O. Moreira-Tamayo,Valerian Mayega,Ran Katz,Ofer Friedman,Oren Eliezer,Elida de-Obaldia,Poras T. Balsara +20 more
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Journal ArticleDOI
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping.
Journal ArticleDOI
A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
TL;DR: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented, which uses a gated-ring-oscillator time-to-digital converter to achieve integrated phase noise of less than 300 fs.
Journal ArticleDOI
A CMOS time-to-digital converter with better than 10 ps single-shot precision
TL;DR: A high-precision CMOS time-to-digital converter IC has been designed based on a counter and two-level interpolation realized with stabilized delay lines that reduces the number of delay elements and registers and lowers the power consumption.
Journal ArticleDOI
Phase-domain all-digital phase-locked loop
TL;DR: In this article, the phase-domain phase-locked loops (PLLs) are replaced by a time-to-digital converter and a simple digital loop filter, and the measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications.