A Fully Integrated 0.13- $\mu$ m CMOS 40-Gb/s Serial Link Transceiver

TLDR: A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology performing half-rate clock and data recovery and a linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening while operating at 39 Gb/s.

Abstract: A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low fTof 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4 times 2.9 mm2 with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 215 -1 PRBS data is 1.85 psrms over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 psrms and the measured BER of the transceiver is less than 10- 14 .