Journal ArticleDOI
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter
Reads0
Chats0
TLDR
In this article, the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops is analyzed.Abstract:
A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.read more
Citations
More filters
Journal ArticleDOI
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs
TL;DR: A digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC that does not require analog building blocks such as operational amplifiers, multi-bit feed-back DACs etc., and retains the scaling friendly properties.
Journal ArticleDOI
A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing
Yongtae Kim,Yong Zhang,Peng Li +2 more
TL;DR: A brain-inspired reconfigurable digital neuromorphic processor (DNP) architecture for large-scale spiking neural networks is presented and the functionality of the proposed DNP architecture is demonstrated by realizing an unsupervised-learning based character recognition system.
Journal ArticleDOI
Carbon nanotube circuit integration up to sub-20 nm channel lengths.
Max M. Shulaker,Jelle Van Rethy,Tony F. Wu,Luckshitha Suriyasena Liyanage,Hai Wei,Zuanyi Li,Zuanyi Li,Eric Pop,Georges Gielen,H.-S. Philip Wong,Subhasish Mitra +10 more
TL;DR: This work demonstrates the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths.
Journal ArticleDOI
CMOS Differential Ring Oscillators: Review of the Performance of CMOS ROs in Communication Systems
TL;DR: In this article, the authors present implementation techniques and performance comparisons of the DRO as a CMOS voltage-controlled oscillator (VCO) in low radio frequency (RF) bands, along with presentation and discussion of a number of circuit approaches.
Journal ArticleDOI
A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS
Xinpeng Xing,Georges Gielen +1 more
TL;DR: A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented, with the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high power efficiency are achieved.
References
More filters
Journal ArticleDOI
Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter
Karthikeyan Reddy,Shanthi Pavan +1 more
TL;DR: In this paper, a lower bound on clock jitter in single-loop low-pass continuous-time delta-sigma (Delta Sigma) modulators employing nonreturn to zero (NRZ) feedback is derived using the discrete-time version of the Bode sensitivity integral.
Journal ArticleDOI
A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators
TL;DR: The proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs, which has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes.
Journal ArticleDOI
Time-referenced single-path multi-bit /spl Delta//spl Sigma/ ADC using a VCO-based quantizer
TL;DR: A single-path multi- bit delta-sigma analog-to-digital converter (/spl Delta//spl Sigma/ ADC) architecture that uses time as a reference for performing multi-bit digital- to-analog conversion in the feedback path that eliminates the need for feedback DAC architectures with static and dynamic component matching.
Proceedings ArticleDOI
A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: In this paper, a combined 5-bit, 1st order noise-shaped quantizer and DEM circuit running at 950MHz based on a multi-phase VCO is presented, where the quantizer structure is the key element in a 3rd order noise shaped ADC with 2nd order loop dynamics and a single opamp.
Journal ArticleDOI
Spectral analysis of time-domain phase jitter measurements
TL;DR: In this paper, the relationship between the time-domain jitter measurements and the power spectrum of the phase jitter is described using fundamental Fourier properties and basic random variables analysis.
Related Papers (5)
A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
M.Z. Straayer,Michael H. Perrott +1 more
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS
M. Park,M.H. Perrott +1 more
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC
Gerry Taylor,Ian Galton +1 more