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Journal ArticleDOI

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

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TLDR
In this article, the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops is analyzed.
Abstract
A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

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Proceedings ArticleDOI

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

TL;DR: A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages and allows for low power and high speed operation and is insensitive to the VCO linearity.
Journal ArticleDOI

A $148fs_{rms}$ Integrated Noise 4 MHz Bandwidth Second-Order $\Delta\Sigma$ Time-to-Digital Converter With Gated Switched-Ring Oscillator

TL;DR: Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators and is analyzed, including non-idealities such as phase noise, mismatch, and PVT variations.
Journal ArticleDOI

SNDR Limits of Oscillator-Based Sensor Readout Circuits

TL;DR: A model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input is proposed, based on periodic steady-state analysis tools to predict the SNR of the oscillators.
Journal ArticleDOI

A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator

TL;DR: A time-domain high-order ΔΣ analog-to-digital converter using voltage-controlled gated-ring oscillator (VC-GRO) and time- domain multi-stage-noise-shaping (MASH) is introduced, which has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process.
Journal ArticleDOI

“Split ADC” Background Linearization of VCO-Based ADCs

TL;DR: A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs and design tradeoffs related to the VCO V-to-f characteristic, lookup table size, and convergence properties of the LMS adaptation loop are discussed.
References
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TL;DR: In this paper, the authors present an overview of current mirror and Opamp design and compensation for single-stage Amplifiers and Current Mirrors, as well as a comparison of the two types of Opamps.
Journal ArticleDOI

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
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Journal ArticleDOI

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

TL;DR: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
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