Journal ArticleDOI
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter
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TLDR
In this article, the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops is analyzed.Abstract:
A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-?m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.read more
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Proceedings ArticleDOI
A 0.03mm 2 , 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO
TL;DR: This work presents an area- and power-efficient realization of a new complementary PWM Gated Ring Oscillator (GRO) that can be used as input stage of an all-digital multi-stage ADC and is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference.
Journal ArticleDOI
Digital compensation method for the path delay mismatches in GRO-TDC
TL;DR: Measurement results show that many calculation errors are corrected by the proposed compensation method reducing the quantization noise power by 10dB at high frequency offset.
All-Digital ADC Design in 65 nm CMOS Technology
TL;DR: This thesis presents the implementation of a VCO-based ADC in STM 65 nm CMOS process technology using digital tools such as ModelSim simulator, Synopsys Design Compiler and Cadence SOC Encounter, which has the advantage of superior time resolution.
Proceedings ArticleDOI
A Two-Step VCO-Based ADC with PWM Pre-coded Coarse Quantizer
TL;DR: A new time-based ADC architecture that employs non-linearity cancellation and swing down scaling techniques to eliminate the non-idealities of the coarse and the fine VCO-based quantizers, respectively is presented.
Proceedings ArticleDOI
Single-Loop Delta-Sigma ADC Using Noise-Coupled VCO Quantizer
TL;DR: A single-loop two-step 3rd order order ADC with voltage-controlled-oscillator (VCO) quantizer employing noise coupling technique is presented, which improves the order of noise-shaping by one or more in VCO quantizer, and makes it power efficient.
References
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Analog Integrated Circuit Design
TL;DR: In this paper, the authors present an overview of current mirror and Opamp design and compensation for single-stage Amplifiers and Current Mirrors, as well as a comparison of the two types of Opamps.
Journal ArticleDOI
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS
Robert Bogdan Staszewski,Khurram Muhammad,Dirk Leipold,Chih-Ming Hung,Yo-Chuol Ho,John Wallberg,C. Fernando,Ken Maggio,Roman Staszewski,T. Jung,Jinseok Koh,S. John,I. Deng,Vivek Sarda,O. Moreira-Tamayo,Valerian Mayega,Ran Katz,Ofer Friedman,Oren Eliezer,Elida de-Obaldia,Poras T. Balsara +20 more
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
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Principles of communications
TL;DR: In addition to stressing fundamental concepts, sections on currently important areas such as spread spectrum, cellular communications, and orthogonal frequency-division multiplexing are provided.
Journal ArticleDOI
A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
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