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Journal ArticleDOI

Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications

TLDR
A nonquasi-static RF model is adopted to analyze the behavior of the proposed ED-TFET in high frequency region and the modeled result shows excellentmatching with the Y-parameters upto 500 GHz.
Abstract
In this paper, we investigate a polarity controlled electrically doped tunnel FET (ED-TFET) based on the bandgap engineering for analog/RF applications. The proposed device exhibits a heavily doped n-type Si-channel with two distinctive gate: 1) control gate (CG) and 2) polarity gate (PG). First, the work function of 4.72 eV is considered for CG and PG to convert the layer beneath CG and PG of intrinsic type. Further, a bias of −1.2 V is applied at PG terminal to induce a p+ region, so that, it follows the similar trend as like a n+-i-p+ gated structure of conventional TFET. To improve the ON-state current of the proposed device, we investigate an interfacing of III–V with IV group material for heterojunction. It shows higher ON-state current in the order of $10^{-4}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio (in the order of $10^{12}$ ) at ${V}_{\sf DS} = 0.7$ V. Further, its higher transconductance ${g} _{m}\approx 1.02$ mS and different RF performance parameters in the range of terahertz, enables its potential for analog/RF applications. However, linearity parameters are analyzed to give the assurance of the device for high-frequency applications. Moreover, a nonquasi-static RF model is adopted to analyze the behavior of the proposed ED-TFET in high frequency region. Based on this, the small-signal parameters were extracted and verified upto 500 GHz. The modeled result shows excellentmatching with the Y-parameters upto 500 GHz.

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Citations
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Journal ArticleDOI

Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

TL;DR: In this article, the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket was investigated for the first time to enhance the carrier tunneling through the source-channel (Si) heterojunction.
Journal ArticleDOI

Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges

TL;DR: In this article, a gate-all-around (GAA) silicon vertical nanowire tunnel field effect transistor (NWTFET) is proposed, and the effects of interface trap charges (ITCs) on dopingless (DL) NW-based device are addressed for the first time.
Journal ArticleDOI

Effect of Interface Trap Charges on Performance Variation of Heterogeneous Gate Dielectric Junctionless-TFET

TL;DR: In this paper, the effect of interface trap charges on the variation of heterogeneous gate dielectric junctionless-tunnel FETs by introducing both donor and acceptor type of localized charges at the semiconductor/insulator interface is investigated.
Journal ArticleDOI

Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance

TL;DR: In this article, a dual-material control gate with dual-oxide tunnel field effect transistor is investigated to overcome the problem of fabrication complexity and to reduce the cost of microelectronic devices.
Journal ArticleDOI

Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

TL;DR: In this article, the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator was investigated.
References
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Journal ArticleDOI

Nanowire transistors without junctions

TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

TL;DR: In this article, a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept was performed using calibrated simulations.
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