Journal ArticleDOI
Design of VLSI CMOS circuits under thermal constraint
W.R. Daasch,C.H. Lim,G. Cai +2 more
TLDR
In this article, the effects of temperature on very large-scale integration design are presented, and an analytical technique is introduced to systematically design and evaluate thermal control mechanisms, such as the dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS).Abstract:
As process technologies continue to scale, the effects of temperature can no longer be neglected. High on-chip temperature causes frequency degradation, increases wasteful leakage power, and lowers device reliability. Therefore, managing on-chip temperature becomes an important design undertaking. In this brief, the effects of temperature on very large-scale integration design are presented, and an analytical technique is introduced to systematically design and evaluate thermal control mechanisms, such as the dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS). Using the energy-delay product (EDP) metric, the DFS is shown to outperform the DCT.read more
Citations
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Journal ArticleDOI
High Rate Data Synchronization in GALS SoCs
TL;DR: A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described, which replaces complex global timing constraints with simpler localized ones and supports high data rates.
Journal ArticleDOI
Processor Speed Control With Thermal Constraints
TL;DR: It is shown that the problem of processor speed control subject to thermal constraints for the environment is a convex optimization problem, and an efficient infeasible-start primal-dual interior-point method for solving the problem is presented.
Journal ArticleDOI
GALDS: a complete framework for designing multiclock ASICs and SoCs
A. Chattopadhyay,Zeljko Zilic +1 more
TL;DR: The Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design.
Proceedings ArticleDOI
A PLA based asynchronous micropipelining approach for subthreshold circuit design
TL;DR: This work proposes a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs, which describes the handshaking protocol, circuit design and logic synthesis issues in this context and yields an energy improvement of about 4times, compared to a traditional network of PLA design.
Proceedings ArticleDOI
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology
Aditya Bansal,Mesut Meterelliyoz,Siddharth Singh,Jung Hwan Choi,Jayathi Y. Murthy,Kaushik Roy +5 more
TL;DR: This work proposes cell-level compact thermal models for standard INV, NAND and NOR gates accounting for the heat transfer across the six faces of a cell and illustrated that temperature-aware timing analysis is imperative, because of high inter-cell temperature gradient.
References
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Book
Feedback Control Systems
TL;DR: This book discusses linearized Dynamic Models, transfer function models of Physical Systems Modeling of Feedback Systems and Controllers, and Multivariable Systems in the Frequency Domain Nonlinear Control Systems.
Proceedings ArticleDOI
New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only)
TL;DR: The talk will describe some of the microarchitecture directions that may lead to more power-efficient and cost-efficient microprocessors and the implications of continued CMOS scaling, as described above, and the new challenges they pose.
Proceedings ArticleDOI
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies
TL;DR: In this article, the authors look at the historical trends of CMOS process technology in the context of past microprocessors and discuss the implications of continued CMOS scaling, as described above, and the new challenges they pose microarchitecture techniques that have exacerbated the power problem.
Proceedings ArticleDOI
A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
Sunit Tyagi,Mohsen Alavi,Robert M. Bigwood,T. Bramblett,J. Brandenburg,W. Chen,B. Crew,Makarem A. Hussein,P. Jacob,C. Kenyon,C. Lo,B. McIntyre,Z. Ma,Peter K. Moon,P. Nguyen,L. Rumaner,R. Schweinfurth,Swaminathan Sivakumar,M. Stettler,Scott E. Thompson,B. Tufts,J. Xu,Simon Yang,M. Bohr +23 more
TL;DR: In this paper, a leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported, where dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V.
Book
Circuit Design for CMOS VLSI
TL;DR: This volume deals with circuit design in an integrated CMOS environment and emphasis is placed on understanding the operation, performance, and design of CMOS integrated circuits.