Journal ArticleDOI
Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications
TLDR
In this article, a double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends is reported.Abstract:
In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by $${\sim }$$~900 %), subthreshold swing characteristics (by $${\sim }$$~12 %) and Drain Induced Barrier Lowering (DIBL) (by $${\sim }$$~56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.read more
Citations
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Journal ArticleDOI
Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric
TL;DR: In this article, a junctionless nanowire TFET with induced source side tunneling realized by a hetero-gate-dielectric (HGD JN-TFET) was proposed.
Journal ArticleDOI
2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect
TL;DR: In this paper, an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs) was proposed, where the channel potential function was obtained by solving 2D Poisson's equation using an evanescent mode analysis with suitable boundary conditions.
Journal ArticleDOI
Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture
Vishal Narula,Mohit Agarwal +1 more
Journal ArticleDOI
Performance Analysis of Gate Electrode Work Function Variations in Double-gate Junctionless FET
TL;DR: In this paper, the performance of the conventional double-gate junctionless FET has been investigated for the range of gate work function from 4.6 eV to 5.1 eV and it has been found that the proposed device shows OFF-current of the order of ~ 10−14 A/µm, ON-to-OFF current ratio of 1010 and sub-threshold slope of 65.6 mV/dec as compared to the conventional single-gate FET.
References
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Journal ArticleDOI
Nanowire transistors without junctions
Jean-Pierre Colinge,Chi-Woo Lee,Aryan Afzalian,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Pedram Razavi,B. O'Neill,Alan Blake,Mary White,Anne-Marie Kelleher,Brendan McCarthy,Richard Murphy +13 more
TL;DR: A new type of transistor in which there are no junctions and no doping concentration gradients is proposed and demonstrated, which has near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.
Journal ArticleDOI
Junctionless multigate field-effect transistor
Chi-Woo Lee,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Jean-Pierre Colinge +5 more
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Journal ArticleDOI
Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs
Greg Leung,Chi On Chui +1 more
TL;DR: In this article, the impact of random dopant fluctuation (RDF) on junctionless FinFET variability was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations.
Journal ArticleDOI
A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs
TL;DR: An analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time in this article, which explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation.
Journal ArticleDOI
Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices
Malgorzata Jurczak,Thomas Skotnicki,R. Gwoziecki,M. Paoli,B. Tormen,P. Ribot,Didier Dutartre,Stephane Monfray,J. Galvier +8 more
TL;DR: In this paper, a new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping, which is the ideal pocket architecture.