Erratum: Analytic Model for the Surface Potential and Drain Current in Negative Capacitance Field-Effect Transistors
TLDR
In this paper, a comprehensive physics-based surface potential and drain current model for the negative capacitance (NC) field effect transistor (FET) is presented, which is aimed to evaluate the potentiality of such transistors for low power switching applications.Abstract:
In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance (NC) region could act as a step-up converter of the surface potential in a metal-oxide-semiconductor structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S <; 60mV/dec). In this paper, a comprehensive physics-based surface potential and a drain current model for the NC field-effect transistor are reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. This paper also sheds light on how operation in the NC region can be experimentally detected.read more
Citations
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Journal ArticleDOI
Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures
Asif Islam Khan,Debanjan Bhowmik,Pu Yu,Sung Joo Kim,Xiaoqing Pan,Ramamoorthy Ramesh,Sayeef Salahuddin +6 more
TL;DR: In this article, a proof-of-concept demonstration of negative capacitance effect in a nanoscale ferroelectric-dielectric heterostructure was presented. But the authors did not consider the effect of temperature on the performance of a bilayer of Pb(Zr0.2Ti0.8)O3 and dielectric SrTiO3.
Journal ArticleDOI
Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching
Jaesung Jo,Changhwan Shin +1 more
TL;DR: In this paper, the authors demonstrate a nearly hysteresis-free sub-60mV/decade subthreshold swing operation in a p-type bulk metaloxide-semiconductor field effect transistor externally connected to a ferroelectric capacitor.
Journal ArticleDOI
Ferroelectric negative capacitance
TL;DR: In this article, the physical mechanisms responsible for negative capacitance (NC) in ferroelectrics are discussed, and different approaches for the optimization of the intrinsic NC response to maximize voltage amplification are discussed.
Journal ArticleDOI
Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics
TL;DR: In this article, the effect of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs was studied.
Journal ArticleDOI
Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices.
TL;DR: Negative capacitance, originating from the dynamics of the stored energy in a phase transition of a ferroelectric material, can achieve the step-up conversion of internal voltage in a metal-oxide-semiconductor device by taking advantage of negative capacitance in a MOS gate stack.
References
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Journal ArticleDOI
Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices
Sayeef Salahuddin,Supriyo Datta +1 more
TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
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TL;DR: In this paper, the use of reactive molecular-beam epitaxy and pulsed-laser deposition to synthesize functional oxides, including ferroelectrics, ferromagnets, and materials that are both at the same time, is described.
Journal ArticleDOI
A continuous, analytic drain-current model for DG MOSFETs
TL;DR: In this article, a continuous analytic currentvoltage model for double-gate MOSFETs is presented, which is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation.
Journal ArticleDOI
Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs
TL;DR: In this paper, a simple but powerful evanescent-mode analysis showed that the length /spl lambda/ over which the source and drain perturb the channel potential, is 1/spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the cylindrical case, in excellent agreement with PADRE device simulations.
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