Journal ArticleDOI
Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits
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TLDR
In this paper, the NBTI/PBTI reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature.Abstract:
In this work, negative bias temperature instability/positive bias temperature instability (NBTI/PBTI) reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature. We have incorporated the NBTI/PBTI $\text{V}_{\mathrm{ T}}$ model in a physics-based SiNW FET Verilog-A compact model for circuit analysis. For the first time, using integrated model, we report time zero variability and BTI reliability of the core logic gates (INVERTER, NAND, and NOR) and read/write stability of 6T SRAM cell. We demonstrate that the delay degradation is circuit topology dependent in which series-connected transistors are more prone to degradation due to PBTI (NBTI) in NAND (NOR) gates. The benchmarking of BTI in SiNW FET with FinFET and planar devices show SiNW have higher degradation, however it can be minimized by using optimized SiNW FET configuration. Further, we show that the SRAM cell design margins are configuration dependent in which impact of BTI degrades the read noise margin (RNM) by 15–30%, and write noise margin (WNM) improves by 5–8% for 10-Year lifetime. We find that the combined impact of time zero variability and BTI reliability degrades the mean value of circuit delay and SRAM RNM stability, however, the degradation is found to be comparable to the reported planar and FinFET data. It is also seen that different configuration increases BTI variability (~5-25% increase) which can be minimized. Using the results, we propose a method to minimize degradation under the influence of variability and reliability by selecting appropriate SiNW FET design configuration. The comprehensive predictive model framework presented here is a valuable tool for variability and reliability-aware SiNW CMOS circuit design and analysis.read more
Citations
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Journal ArticleDOI
CMOS Reliability From Past to Future: A Survey of Requirements, Trends, and Prediction Methods
TL;DR: In this article , a comprehensive look at trends in IC reliability and investigates the methods used to predict failures is presented, along with reliability requirements for different markets and review of key aging mechanisms affecting modern ICs.
Journal ArticleDOI
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation
Journal ArticleDOI
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation
Proceedings ArticleDOI
Negative Bias Temperature Instability Analysis of a 15 nm p-channel Junctionless Fin Field Effect Transistor (p-JLFinFET)
TL;DR: In this article , the reliability issue of Negative Bias Temperature Instability (NBTI) on a 15 nm p-channel junctionless Fin Field Effect Transistor (p-JLFinFET) was analyzed.
Comprehensive Reliability Analysis of 22nm FDSOI SRAM from Device Physics to Deep Learning
Om Prakash,Rodion Novkin,Virinchi Roy Surabhi,Prashanth Krishnamurthy,Ramesh Karri,Farshad Khorrami,Hussam Amrouch +6 more
TL;DR: In this article , the authors investigate the impact of device variability and transistor aging on the data integrity of SRAM cells implemented using 22nm FDSOI technology node and demonstrate that short-term aging (i.e., when aging effects are combined with voltage scaling) results in a noticeable accuracy drop.
References
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Journal ArticleDOI
Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing
TL;DR: The negative bias temperature instability (NBTI) commonly observed in p-channel metaloxide-semiconductor field effect transistors when stressed with negative gate voltages at elevated temperatures is discussed in this article.
Journal ArticleDOI
The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps
Tibor Grasser,Ben Kaczer,Wolfgang Goes,Hans Reisinger,Th. Aichinger,Ph. Hehenberger,P.-J. Wagner,Franz Schanovsky,Jacopo Franco,Maria Toledano Luque,Michael Nelhiebel +10 more
TL;DR: In this paper, the bias temperature instability (BTI) has been known since the 1960s, and a large number of detailed recovery studies have been published, showing clearly that the reaction-diffusion mechanism is inconsistent with the data.
Journal ArticleDOI
Negative bias temperature instability: What do we understand?
TL;DR: The general conclusion is that although much is understood about NBTI, several aspects are poorly understood.
Journal ArticleDOI
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology
TL;DR: A unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects is presented, and it is demonstrated that the proposed method very well predicts the degradation.
Proceedings ArticleDOI
Origin of NBTI variability in deeply scaled pFETs
Ben Kaczer,Tibor Grasser,Ph. J. Roussel,Jacopo Franco,Robin Degraeve,Lars-Ake Ragnarsson,Eddy Simoen,Guido Groeseneken,Hans Reisinger +8 more
TL;DR: In this article, the similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs.