Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier Layers

TLDR: In this paper, the authors investigated the logic circuit behavior of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length L g = 20 and 30 nm.

Abstract: We investigate the logic circuit behaviour of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length L g = 20 and 30 nm. Rise and fall time, noise margin of hybrid CMOS inverters and frequency of oscillations, energy-delay product of 3-stage ring oscillators comprising hybrid CMOS inverters have been investigated to evaluate the performance of the proposed CMOS device. Our findings show a significant amount of reduction of 92.2 and 82.5% for rise and fall time, respectively, in case of proposed hybrid inverter, compared with the corresponding values for equivalent Si CMOS at L g = 30 nm. Oscillation frequency of a 3-stage ring oscillator is found to be 264% higher when compared with its Si counterpart. Also there is an improvement of 17.8 and 77.4% in power-delay and energy-delay product, respectively, for hybrid CMOS inverters in comparison with their equivalent Si counterparts for a channel length of 30 nm. Similar trend is observed in case of channel length of 20 nm.