Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell

TLDR: This paper evaluates the impact of litho variations on the yield of SRAM cells on the basis of different metrics for the stability, readability and write-ability used to define parametric yield.

Abstract: To ensure the continuation of the scaling of VLSI circuits fo r years to come, the impact of litho on performance of logic circuits has to be understood. Using different litho options such as single or double patterning may result in different process variations. This paper evaluates the impact of litho variations on the yield of SRAM cells. The exploration is focused on six transistor SRAM cells (6T SRAM) which have to be printed with the highest possible density with good yield to limit system’s cost. Consequently, these cells im pose the most stringent constraints on litho techniques. An SRAM cell is yielding if it operates correctly like a memory device (functional yield) and the performance of the cell is in spec for the chosen architecture (parametric yield). In this paper, different metrics for the stability, readability and write-ability are used to define parametric yield. The most important litho-induced variations are illumination dose, focus, overlay mismatch and line-edge roughness. Unwanted opens and shorts in the printed patterns caused by the process variations will cause the cell to malfunction. These litho-induced variations also cause dimension offsets, i.e. variations on transistors’ widths and lengths, which reduces the stability, readability and write-ability of the cell, thereby increasing parametric yield loss. Litho simulators are coupled with a device parasitic extractor to simulate the impact of the litho offsets on the yield of the SRAM cell. Based on these simulations guidance will be provided on the choice between different litho options. Keywords: Yield, SRAM, line-width roughness, CD uniformity, overlay