Proceedings ArticleDOI
Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS
K. Kuhn
- pp 471-474
TLDR
In this article, the authors present an overview of process variation effects, including examples of mitigation strategies and test methods for 45 nm and 65 nm RDFs, including SRAM matching and interconnect variation.Abstract:
This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45 nm and 65 nm RDF. SRAM matching and interconnect variation is discussed for both 65 nm and 45 nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65 nm and 45 nm products.read more
Citations
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Journal ArticleDOI
Process Technology Variation
K. Kuhn,Martin D. Giles,D. Becher,Pramod Kolar,A. Kornfeld,Roza Kotlyar,S. T. Ma,A. Maheshwari,S. Mudanai +8 more
TL;DR: The importance of process variation in modern transistor technology is discussed, front-end variation sources are reviewed, device and circuit variation measurement techniques are presented, and recent intrinsic transistor variation performance from the literature is compared.
Proceedings ArticleDOI
45nm High-k + metal gate strain-enhanced transistors
C. Auth,Annalisa Cappellani,J.-S. Chun,A. Dalis,Alison Davis,Tahir Ghani,G. Glass,Timothy E. Glassman,Michael K. Harper,Michael L. Hattendorf,P. Hentges,S. Jaloviar,Subhash M. Joshi,Jason Klaus,K. Kuhn,D. Lavric,M. Lu,H. Mariappan,Kaizad Mistry,B. Norris,Nadia M. Rahhal-Orabi,Pushkar Ranade,J. Sandford,Lucian Shifren,V. Souw,K. Tone,F. Tambwe,A. Thompson,D. Towner,T. Troeger,P. Vandervoorn,Charles H. Wallace,J. Wiedemer,Christopher J. Wiegand +33 more
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Proceedings ArticleDOI
The new era of scaling in an SoC world
TL;DR: The new era of microprocessor scaling is a system-on-a-chip approach that combines a diverse set of components using adaptive circuits, integrated sensors, sophisticated power-management techniques, and increased parallelism to build products that are many-core, multi- core, and multi-function.
Journal ArticleDOI
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
TL;DR: The prototype employs a deep in-memory architecture (DIMA), which enhances both energy efficiency and throughput over conventional digital architectures via simultaneous access of multiple rows of a standard 6T bitcell array (BCA) per precharge, and embedding column pitch-matched low-swing analog processing at the BCA periphery.
Proceedings ArticleDOI
An energy-efficient vlsi architecture for pattern recognition via deep embedding of computation in sram
TL;DR: System-level simulations incorporating various deterministic errors from analog signal chain demonstrates the limited accuracy of analog processing does not significantly degrade the system performance, which means the probability of pattern detection is minimally impacted.
References
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Journal ArticleDOI
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
TL;DR: This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.
Journal ArticleDOI
Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study
TL;DR: In this paper, a 3D simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented.
Journal ArticleDOI
Modeling statistical dopant fluctuations in MOS transistors
TL;DR: In this paper, the impact of statistical dopant fluctuations on the threshold voltage and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling, and it is found that the average V/sub T/-shift is positive for long, narrow devices, and negative for short, wide devices.
Proceedings ArticleDOI
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
Jack Portland Kavalieros,B. Doyle,Suman Datta,G. Dewey,Mark Beaverton Doczy,B. Jin,D. Lionberger,Matthew V. Metz,Willy Rachmady,Marko Radosavljevic,Uday Shah,Nancy M. Zelick,R. Chau +12 more
TL;DR: In this paper, the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering are combined with high performance NMOS and PMOS trigate transistors.
Journal ArticleDOI
Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations
TL;DR: In this paper, the intrinsic threshold voltage fluctuations induced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional numerical simulations on a statistical scale.