Journal ArticleDOI
Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure
TLDR
In this paper, a generalized 2D analytical model of gate threshold voltage for multiple material gate tunneling FET (TFET) structures is derived, which includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters.Abstract:
A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.read more
Citations
More filters
Journal ArticleDOI
Influence of Threshold Voltage Performance Analysis on Dual Halo Gate Stacked Triple Material Dual Gate TFET for Ultra Low Power Applications
M. Venkatesh,N. B. Balamurugan +1 more
TL;DR: In this paper, a threshold voltage modeling based gate and channel engineering is developed analytically for Dual Halo Gate Stacked Triple Material Dual Gate Tunnel FET (DH-GS-TM-DG-TFET) with effective surface charge.
Journal ArticleDOI
An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices
TL;DR: The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption, and enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature.
Journal ArticleDOI
Implementation of linearly modulated work function A σ B 1-σ gate electrode and Si 0.55 Ge 0.45 N+ pocket doping for performance improvement in gate stack vertical-TFET
Girish Wadhwa,Jeetendra Singh +1 more
TL;DR: In this paper, the characteristics of linearly graded work function (LGW) by utilizing the composition of binary metal alloy AσB1−σ gate electrode and Si-Si0.55Ge0.45 middle N+ pocket heterojunction at the interface of source and channel is explored in the high-k gate stack vertical-TFET (GS-VTFET).
Journal ArticleDOI
Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices
TL;DR: In this article, the authors investigated a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously improve the RF performance.
Journal ArticleDOI
Design and Analysis of Tunnel FET for Low Power High Performance Applications
TL;DR: This paper highlights and compares the best TFET designs proposed in the literature namely: Double gate Si-based TFET, InAs TFET device and III-V semiconductor (GaAs1-xSbx-InAs) basedTFET device.
References
More filters
Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Proceedings ArticleDOI
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope
TL;DR: In this paper, a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS < 60 mV/dec was experimentally demonstrated.
Journal ArticleDOI
Tunnel field-effect transistor without gate-drain overlap
TL;DR: In this article, the authors generalized the tunnel field effect transistor configuration by allowing a shorter gate structure, which is especially attractive for vertical nanowire-based transistors, and demonstrated with device simulations that the more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.
Journal ArticleDOI
Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor
TL;DR: In this paper, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage.