Journal ArticleDOI
Strained Silicon Nanowire Transistors With Germanium Source and Drain Stressors
Tsung-Yang Liow,Kian-Ming Tan,Rinus T. P. Lee,Ming Zhu,Ben Lian-Huat Tan,N. Balasubramanian,Yee-Chia Yeo +6 more
TLDR
In this paper, pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm were demonstrated.Abstract:
We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.read more
Citations
More filters
Patent
Strained semiconductor nanowire
TL;DR: In this article, at least one semiconductor nanowire is laterally abutted by a pair of semiconductor pad portions over an insulator layer, and a temporary fill material is deposited over the at least single semiconductor wire and planarized to physically expose the top surfaces of the pair of pad portions.
Patent
Techniques for integration of Ge-rich p-MOS source/drain
TL;DR: In this article, techniques for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to reduce contact resistance have been discussed, and the techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive ge-rich materials.
Patent
P-FET mit einem verspannten Nanodraht-Kanal und eingebetteten SiGe-Source- und Drain-Stressoren und Verfahren
TL;DR: In this paper, the author verfahren zum herstellen eines Feldeffekttransistors (FET), das die folgenden Schritte umfasst: das dotierte Substrat ein p++-dotiertes Siliciumsubstrat, wobei andere Teile des Nanodrahtes freiliegend bleiben.
Patent
A p-FET with a strained nanowire channel and embedded SiGe source and drain stressors
TL;DR: In this paper, techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided.
References
More filters
Journal ArticleDOI
Kinetic pathway in Stranski-Krastanov growth of Ge on Si(001).
TL;DR: The transition from 2D to 3D growth of Ge on Si(001) has been investigated with scanning tunneling microscope and a metastable 3D cluster phase with well-defined structure and shape is found.
Journal ArticleDOI
Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness
TL;DR: In this paper, a six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer.
Journal ArticleDOI
Analysis of the parasitic S/D resistance in multiple-gate FETs
TL;DR: In this article, the authors analyzed the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, s/D geometry-based analytical model, which was validated using three-dimensional device simulations and experimental results.
Proceedings ArticleDOI
5nm-gate nanowire FinFET
Fu-Liang Yang,Di-Hong Lee,Hou-Yu Chen,Chang-Yun Chang,Sheng-Da Liu,Cheng-Chuan Huang,Tang-Xuan Chung,Hung-Wei Chen,Chien-Chao Huang,Yi-Hsuan Liu,C.C. Wu,Chi-Chun Chen,Shih-Chang Chen,Ying-Tsung Chen,Ying-Ho Chen,C.H. Chen,Bor-Wen Chan,Peng-Fu Hsu,Jyu-Horng Shieh,Han-Jan Tao,Yee-Chia Yeo,Yiming Li,Jam-Wem Lee,Pu Chen,Mong-Song Liang,Chenming Hu +25 more
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Journal ArticleDOI
Nanoscale FinFETs with gate-source/drain underlap
TL;DR: In this article, the authors show that gate-source/drain (G-S/D) underlap can be achieved via large, doable straggle in the S-D fin-extension doping profile.