Journal ArticleDOI
Strained Silicon Nanowire Transistors With Germanium Source and Drain Stressors
Tsung-Yang Liow,Kian-Ming Tan,Rinus T. P. Lee,Ming Zhu,Ben Lian-Huat Tan,N. Balasubramanian,Yee-Chia Yeo +6 more
TLDR
In this paper, pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm were demonstrated.Abstract:
We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.read more
Citations
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Patent
A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors
TL;DR: In this article, techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided.
Journal ArticleDOI
Strain effects on three-dimensional, two-dimensional, and one-dimensional silicon logic devices: Predicting the future of strained silicon
TL;DR: In this article, the effects of strain-induced band splitting and band warping on the modification of the average conductivity effective mass and carrier scattering rates were evaluated using a classification scheme based on carrier confinement type (electrostatic and spatial) and the degrees of freedom of the mobile carriers.
Journal ArticleDOI
Investigation of sub-10nm cylindrical surrounding gate germanium nanowire field effect transistor with different cross-section areas
TL;DR: In this article, germanium nanowires with different cross-sectional areas are considered as the channel of a cylindrical surrounding gate field effect transistors (CSG-FETs) and the electronic properties of them are calculated through the density functional method and Slater-Koster (SK) tight binding model.
Patent
Techniques for integration of ge-rich p-mos source/drain contacts
TL;DR: In this article, techniques for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to reduce contact resistance have been discussed, and the techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive ge-rich materials.
Journal ArticleDOI
Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications
TL;DR: In this paper, an analytical model of the threshold voltage and drain current for gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field effect transistors (MOSFETs) was proposed.
References
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Journal ArticleDOI
Critical thickness enhancement of epitaxial SiGe films grown on small structures
TL;DR: In this paper, SiGe films with various thicknesses and compositions were epitaxially grown around vertical fins and horizontal membranes with thicknesses as thin as 12nm to demonstrate the concepts.
Journal ArticleDOI
Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors
Wei-Wei Fang,Navab Singh,Lakshmi Kanta Bera,H. S. Nguyen,S.C. Rustagi,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TL;DR: In this article, the authors demonstrate the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique using the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs.
Journal ArticleDOI
Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain
TL;DR: In this article, a p-channel ultrathin body (UTB) MOSFET with body thickness down to 4 nm and raised source and drain (S/D) using selectively deposited Ge are demonstrated for the first time.
Journal ArticleDOI
Hydrogen-surfactant mediated growth of Ge on Si(001)
TL;DR: Park et al. as mentioned in this paper proposed a method for surface analysis in nanometer scale and applied it in the field of chemistry at the Korea Advanced Institute of Science and Technology (KAIT).
Proceedings ArticleDOI
Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement
Tsung-Yang Liow,K. M. Tan,Rinus T. P. Lee,Anyan Du,Chih-Hang Tung,Ganesh S. Samudra,Won Jong Yoo,N. Balasubramanian,Yee-Chia Yeo +8 more
TL;DR: In this paper, a 25 nm gate length LG tri-gate FinFET with Si0.99C0.01 source and drain (S/D) regions is presented.