IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 6, NOVEMBER 2014 1029
Top–Down Fabrication of Gate-All-Around
Vertically Stacked Silicon Nanowire FETs
With Controllable Polarity
Michele De Marchi, Student Member, IEEE, Davide Sacchetto, Member, IEEE, Jian Zhang, Student Member, IEEE,
Stefano Frache, Member, IEEE, Pierre-Emmanuel Gaillardon, Member, IEEE, Yusuf Leblebici, Fellow, IEEE,
and Giovanni De Micheli, Fellow, IEEE
Abstract—As the current MOSFET scaling trend is facing strong
limitations, technologies exploiting novel degrees of freedom at
physical and architecture level are promising candidates to en-
able the continuation of Moore’s predictions. In this paper, we
report on the fabrication of novel ambipolar Silicon nanowire
(SiNW) Schottky-barrier (SB) FET transistors featuring two in-
dependent gate-all-around electrodes and vertically stacked SiNW
channels. A top–down approach was employed for the nanowire
fabrication, using an e-beam lithography defined design pattern.
In these transistors, one gate electrode enables the dynamic con-
figuration of the device polarity (n- or p-type) by electrostatic dop-
ing of the channel in proximity of the source and drain SBs. The
other gate electrode, acting on the center region of the channel
switches ON or OFF the device. Measurement results on silicon
show I
on
/I
off
> 10
6
and subthreshold slopes approaching the
thermal limit, SS ≈ 64 mV/dec (70 mV/dec) for p(n)-type oper-
ation in the same physical device. Finally, we show that the XOR
logic operation is embedded in the device characteristic, and we
demonstrate for the first time a fully functional two-transistor
XOR gate.
Index Terms—Ambipolar transistor, Bosch process,double-gate,
dual-gate, e-beam lithography, gate-all-around (GAA), polarity
control, silicon nanowire (SiNW), top-down fabrication, XOR
logic gate.
I. INTRODUCTION
B
ULK CMOS technologies are predicted to face crucial
technological challenges in the next decade. At the same
time, novel devices such as Silicon nanowire field-effect transis-
tors (SiNWFETs) and Carbon nanotube field-effect transistors
(CNTFETs), which do not suffer from the same constraints,
are receiving increasing attention due to their promising char-
acteristics, such as quasi-ballistic transport, steep subthreshold
slopes and 1-D channel geometry [1], [2].
Manuscript received November 5, 2013; revised May 2, 2014 and August 25,
2014; accepted September 30, 2014. Date of publication October 14, 2014; date
of current version November 6, 2014. The review of this paper was arranged by
Associate Editor I. O’Connor.
M. De Marchi, J. Zhang, P.-E. Gaillardon, and G. De Micheli are with the
Laboratory of Integrated Systems,
´
Ecole Polytechnique F
´
ed
´
erale de Lausanne,
1015 Lausanne, Switzerland (e-mail: michele.demarchi@epfl.ch; jian.zhang@
epfl.ch; pierre-emmanuel.gaillardon@epfl.ch; giovanni.demicheli@epfl.ch).
D. Sacchetto and Y. Leblebici are with the Microelectronic Systems Labora-
tory,
´
Ecole Polytechnique F
´
ed
´
erale de Lausanne, 1015 Lausanne, Switzerland
(e-mail: davide.sacchetto@epfl.ch; yusuf.leblebici@epfl.ch).
S. Frache is with the Electronics and Telecommunications Department, Po-
litecnico di Torino, 10129 Torino, Italy (e-mail: sfrache@gmail.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2014.2363386
Fig. 1. (a) 3-D view of the complete device. S/D pillars supporting a vertical
stack of nanowires are shown in green. The GAA polarity gate, covering the
side regions of the channel is shown in violet, while the central control gate is
shown in red. (b) Fabricated device dimensions.
Specifically, this paper extends our work on the fabrication of
vertically stacked double-gate (DG) Silicon nanowire (SiNW)
FETs [3], featuring two gate-all-around (GAA) electrodes (see
Fig. 1). Vertically stacked GAA SiNWs represent a natural evo-
lution of FinFET structures, providing the best geometry for
electrostatic control over the channel, and consequently, su-
perior scalability properties [4], [5]. In the described device,
one gate electrode, the control gate (CG), acts conventionally
by bulk switching ON and OFF the channel. The other elec-
trode, the polarity gate (PG), acts on the side regions of the
channel, in proximity to the source / drain (S/D) Schottky junc-
tions, switching the device polarity dynamically between n- and
p-type. Measured devices show subthreshold slopes of
64 mV/dec and 70 mV/dec, respectively, for the p-type and
n-type conduction branches in the same physical device. More-
over, I
on
/I
off
values range from 10
6
to 10
7
, respectively, for the
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1030 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 6, NOVEMBER 2014
p-type and n-type conduction branches still in the same device.
The applied voltage ranges for the PG and CG are comparable.
Thanks to the compatible CG and PG threshold voltages,
these devices can exploit both gates as logic inputs, enabling
the design of compact cells that implement XOR more effi-
ciently than in CMOS [6], [7]. Recent works on logic design
have shown that using ambipolar DG devices requires fewer
resources than the conventional CMOS both using static [8],
[9] and dynamic logic [10] approaches. Moreover, implementa-
tion of Sea-of-Gate architectures with DG-SiNW devices [11]
can reduce fabrication costs by providing efficient circuit imple-
mentations and maintaining a high level of regularity in circuit
layouts.
Early transistors demonstrating polarity control employed
bottom–up fabricated SiNWs [12], [13] and carbon nanotubes
[14] as channel material. However, researchers are still encoun-
tering difficulties in selection and placement of these structures
on the final substrate, these techniques still requiring a techno-
logical breakthrough to be employed in current ultralarge-scale
circuit integration (ULSI). In this paper, we use a top–down ap-
proach to fabricate the SiNWs from a lithographically defined
mask, enabling large-scale fabrication of arrays of vertical stacks
of nanowires, without requiring complex transfer procedures of
pregrown nanowires on a final substrate.
This paper is organized as follows: Section II is an overview
on the transition from bulk MOSFETs to GAA-NWFET devices.
Section III presents the proposed device structure and details on
its fabrication. Section IV presents characterization results and
introduces a TCAD model of the device. Section V shows some
measured logic circuits built with our devices and presents some
performance evaluation using the device TCAD model. Finally,
Section VI discusses some future improvements and directions
of this paper and Section VII concludes the paper.
II. B
ACKGROUND
In recent years, the trend toward device miniaturization,
aimed at increasing performance while reducing variability and
circuit power consumption, has led to the introduction of 3-D
device channel structures, such as the two-gate, Ω-gate, and Fin-
FET transistors [15]. These increasingly sophisticated channel
geometries enhance the electrostatic control of the gate over
the device channel, reducing short channel effects (SCEs) [1],
[16] and allowing more aggressive scaling of the device dimen-
sions. If we further optimize the channel geometry, we obtain
the nanowire FET, with a GAA electrode wrapped around the
nanowire surface. This geometry maximizes the surface to vol-
ume ratio of the channel to gate interface, thus optimizing the
channel electrostatics [17], [18]. Devices with this geometry
reach high I
on
/I
off
ratios and steep subthreshold slopes (SS)
approaching the thermal limit of ∼ 60 mV/dec.
However, another challenge at and below the 22-nm tech-
nology node is the fabrication of abrupt chemical doping pro-
files. Specifically, devices’ active regions at these technology
nodes may contain 100 or less dopant atoms, and variations of
even small percentages may result in faulty circuit applications.
As an alternative to chemically doped transistors, silicide-based
Fig. 2. Conceptual band diagrams for the ambipolar double gate device. Four
cases are shown, describing the four combinations of high / low bias for the
polarity gate and control gate of the device. Electron paths are shown with red
arrows / crosses, hole paths are shown with blue arrows / crosses.
Schottky barrier (SB) CNTFETs [19], [20] and SiNWFETs [21]
have been proposed due to their relatively low-temperature pro-
cessing, simpler fabrication and sharp S/D silicide to channel
interfaces [22], [23]. These devices are fabricated by creating
two metal or silicide S/D contacts at the sides of a lowly doped or
intrinsic channel. Due to the presence of S/D SBs, these devices
typically have an ambipolar behavior, showing a superposition
of hole and electron transport characteristics. Moreover, SS val-
ues in SB devices are very degraded due to the carrier injection
through the S/D barriers.
In order to overcome these limitations, devices exploiting a
second gate structure (polarity gate) have been proposed [12]–
[14]. This second gate acts on the channel band structure in
proximity of S/D contacts. Fig. 2 shows a conceptual band di-
agram of such device for different regions of operation (see
Section IV-A). The effect of the PG is to induce an electrostatic
doping of the side regions of the channel, allowing only one
carrier type through the channel at any given time. As we will
further explain in the following sections, this feature not only
improves device characteristics and performance, but provides
an additional degree of freedom at circuit design level by provid-
ing a transistor, which can be polarized at runtime. Specifically,
the same transistor structure can be replicated in an array and
used to produce logic circuits without the need of separate p and
n wells in the circuit layouts. Table I gives an overview of the
state-of-the-art of controllable polarity devices. Note that we
define symmetric a device whose n-type characteristic matches
its p-type characteristic in I
d
current ranges and SS values.
Stimulated by the demonstration of devices which could per-
form as n- or p-type depending on their bias configuration,
various works at circuit design level have focused on exploit-
ing this added configurability. Static [6], [8], [24] and dynamic
logic [10], [25] architectures based on configurable devices have
shown an advantage with respect to the conventional CMOS by
implementing circuits with reduced area occupation and lower
delay. Static logic design using DG-FET is particularly attrac-
tive, as it is based on the robust complementary logic typical of
CMOS, while exploiting the increased expressive power given
by DG-FETs, which enable the construction of XOR logic gates
DE MARCHI et al.: TOP–DOWN FABRICATION OF GATE-ALL-AROUND VERTICALLY STACKED SILICON NANOWIRE FETS 1031
TABLE I
S
TATE -OF-THE-ART FOR NANOWIRE /NANOTUBE DEVICES WITH FULL /PARTIAL POLARITY CONTROL BY MEANS OF A POLARITY GAT E
Ref. Device Type Approach Device length Wire
diameter
V
pg
range V
cg
range I
on
/I
off
Subthreshold Slope
[12] Single SiNWFET,
Ω-gate (CG),
Substrate (BG)
Bottom–up 500 nm (gate) 40 – 100 nm −15 V (p-type)
−5V(OFF)
−2–2V ≈10
7
(p-type) ≈140 mV/dec
(p-type)
[26] Single SiNWFET,
Ω-gate (CG),
Substrate (BG)
Top–down 28 μm (channel)
2 μm(gate)
60 nm −10V–10V −4V
(p-type) 4V
(n-type)
≈10
6
(n-type)
≈10
4
(p-type)
≈80 mV/dec
(n-type) >2000
mV/dec (p-type)
[27] Single SiNWFET,
Ω-gate (CG), Ω-gate
(BG)
Bottom–up ≈1 μm
(channel)
220 nm (gate
regions)
20 nm V
pg
=2V,V
d
=2V
(n-type) V
pg
=−2V,
V
d
=−2 V (p-type)
−2–2V ≈10
7
(n-type)
≈10
9
(p-type)
≈150 mV/dec
(n-type) ≈150
mV/dec (p-type)
[14] Single CNTFET,
Ω-gate (CG),
Substrate (BG)
Bottom–up 300 nm
(channel)
≈1.4 nm V
pg
=1.6 V,
V
d
=0.6 V (n-type)
V
pg
=−2V,
V
d
=−0.6 V (p-type)
−2–2V ≈10
3
(n-type)
≈10
4
(p-type)
≈63 mV/dec
(p-type)
This
study
Stacked SiNWs,
GAA (CG), GAA
(BG)
Top–down 400 nm
(channel)
100 nm (gate
regions)
20–30nm −1V – 4V (n-type)
−4V – 0V (p-type)
−1–4V ≈10
7
(n-type)
≈10
6
(p-type)
≈70 mV/dec
(n-branch) ≈64
mV/dec (p-branch)
Our device shows a high level of symmetry between n and p operation in terms of SS, I
on
/I
off
and input voltages, combined with a top–down fabrication approach enabling
large-scale integration.
with only four transistors instead of the eight transistors required
in the CMOS implementation.
An additional note concerns the fine tuning of device channel
width in these novel devices (based on fin or nanowire struc-
tures), which is more challenging than in bulk MOSFET tech-
nologies. For example, in commercial FinFETs, two full fins
have to be employed to obtain a W =2 device. As further
explained in Section V-B, DG-FET devices enable shorter pull-
up(down) network transistor series in the case of binate functions
(e.g., XOR), thus further reducing the need of large transistor
sizing. Moreover, technology tuning to obtain symmetric p- and
n-type characteristics in the same device is also beneficial to the
width sizing constraint, producing logic gates with symmetrical
output characteristics even when using the same geometrical
transistor sizing in pull-up(down) networks.
III. D
EVICE STRUCTURE AND FABRICATION
Fig. 1(a) shows the conceptual structure of the fabricated de-
vices. A vertical stack of horizontal nanowires is first fabricated
by dry etching of an SOI device layer (shown in green in the fig-
ure). These nanowire stacks are sustained by two silicon pillars
at the two extremities. The nanowire stacks can be built in a reg-
ular and compact fashion by sharing pillars between adjacent
transistors (see Section III-B). Note that the presence of two
gate contacts along for each device may increase circuit routing
complexity. As described in [11], however, this back-to-back
transistor structure effectively minimizes routing congestion in
complex logic cells. As described in the next section, GAA
polarity and control gates (respectively, violet and red in the
Fig. 1) are then added to the structure. Finally, nickel is intruded
by controlled thermal annealing in the source and drain pillar
structures in order to form SBs partially overlapping the side PG
regions. In order to enable large scale integration of the devices,
the process flow is fully implemented in a top–down fashion,
using three e-beam lithography steps.
Fig. 3. DRIE applied to nanowire fabrication. (a) Photoresist (PR) mask is
applied on crystalline silicon; (b) physical/chemical SF
6
etching is applied,
creating an undercut below the mask pattern; (c) conformal thin passivation is
applied using C
4
F
8
gas; (d) vertically accessible surface passivation is readily
removed by the partly anisotropic SF
6
etching; (e) finally, a new undercut is
produced by chemical etching by the SF
6
, leading to (f) new nanowire.
A. Nanowire Fabrication
The nanowires were fabricated in a top–down fashion, ex-
ploiting a single adapted deep reactive ion etching (DRIE) pro-
cessing step [28], [29] to form the device channels. Originally
developed to produce high aspect ratio vertical structures, the
DRIE process provides a fast and ULSI compatible method to
fabricate nanowire stacks. The process is illustrated in Fig. 3. A
Si dry etching step (SF
6
plasma) is interleaved with a passiva-
tion step (C
4
F
8
plasma). These two steps are cycled a number
of times, ultimately creating a number of horizontal grooves
reproducing a photoresist pattern. If the pattern consists of a
thin line, around 50 ÷ 100 nm in width, the grooves descend-
ing from the two sides of the pattern meet, and a vertical stack
1032 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 13, NO. 6, NOVEMBER 2014
Fig. 4. SEM/FIB cross sections of fabricated devices, showing the (a)
nanowire stack with 8-nm gate oxide and 50-nm thick conformal polysilicon
GAA structure; and (b) optimized d<20-nm stacked nanowires.
of horizontal nanowires is formed. By changing the number
of etching cycles, therefore, the number of nanowires in the
stack can be customized. Specifically, in our process, we de-
signed channels consisting of ∼ 350 nm long vertical stacks
of four nanowires on a slightly p-doped (∼ 10
15
atoms/cm
3
)
SOI substrate. Note that these dimensions were chosen to relax
constraints in the subsequent process steps. No process-specific
physical constraints would limit device scaling differently than
in similar state-of-the-art devices such as FinFETs. Finally, the
wires are sustained by pillar structures at both ends, produced
by photoresist squares. The pillars act as source and drain con-
tacts for the transistors [in green in Fig. 1(a)] Fig. 4 shows two
SEM/FIB cross sections of the nanowire stacks. In Fig. 4(a),
rhombohedral shape wires are shown, surrounded by the 50-nm
conformal polysilicon gate material. In Fig. 4(b), the DRIE pro-
cess was optimized to obtain thinner, more round nanowires.
Specifically, lower C
4
F
8
gas flow rate will produce more round
wires [29], while the nanowire thickness can be tuned by ac-
cordingly reducing the original photoresist pattern. Although the
DRIE process has to be tuned for different cases (e.g., to reduce
notching when using a SOI substrate), nanowire fabrication re-
liability is high. We estimate the number of damaged/broken
wires to be 1%.
B. Polarity and Control Gate Formation
After the stacks were formed, a first gate oxide (∼8nm)
was produced by self-limiting oxidation [30] of the nanowires
followed by a 50-nm conformal polysilicon layer deposition.
A rather thick oxide was deliberately chosen to reduce risk
of leakage after the final silicidation step in this first device
demonstration. At this point, the polarity gate was patterned all-
around the nanowires after e-beam lithography. Fig. 5(a) shows
an SEM image of the devices after patterning of the first gate
structure. The transistors are fabricated in couples, sharing a S/D
pillar. This design was chosen due to its increased mechanical
stability in comparison with an isolated device, and its low area
occupation when employed to build regular circuit architectures
[31]. Hence, a second 8-nm oxidation and 50-nm polysilicon
deposition was performed. The CG structure is self-aligned to
the PG, and acts on the uncovered center region of the nanowires
of Fig. 5(a). As shown in the SEM image in Fig. 5(b), three
gated regions are obtained, each approximately 100 ÷ 120 nm
long and electrically isolated by the CG gate oxidation.
Fig. 5. Tilted SEM views of an array of fabricated devices (a) before creation
of the control gates and (b) after addition of the control gates. S/D pillars and
nanowires (green), PG (violet) and CG (red) are shown.
Fig. 6. Linear plot of a measured device. The device connections are shown in
the inset. n- and p-type conduction is selected by different V
pg
biases. Currents
in the p-type and n-type branch are comparable. Asymmetry is due to the
nonperfectly midgap contact workfunction.
After the formation of the gates, a 25-nm low-stress silicon
nitride spacer was deposited conformally and etched anisotrop-
ically to isolate the structures. A nickel layer was deposited by
evaporation; subsequently, annealing (20
at 200
◦
C + 20
at
300
◦
C + 20
at 200
◦
C) was performed to produce NiSi at the
S/D and gate contacts. As further described in Section IV-B,
NiSi was chosen as it features a near midgap workfunction with
respect to silicon, further providing low interface defects at the
NiSi to silicon channel junctions. Finally, unreacted nickel was
removed by selective wet etching in hot piranha solution.
IV. D
EVICE CHARACTERIZATION
This section presents electrical measurements showing the
device operation at different gate biases. SB height for the
nickel silicide contacts at the sides of the nanowire channels
is extracted. Finally, a TCAD model of the fabricated devices is
introduced and validated against the measured data.
A. Polarity Control Operation
Polarity control by means of the PG is illustrated in Figs. 6 and
7. Linear and semilogarithmic I
d
− V
cg
plots of the same device
are provided at different PG biases. As introduced earlier, Fig. 2
presents a band diagram along the device channel, showing the
carriers involved in device operation at different CG and PG
biases. A positive PG bias allows electron conduction at the S/D
SBs, setting the device to n-type, while low PG bias makes holes
become the majority carriers, producing a p-type conduction
DE MARCHI et al.: TOP–DOWN FABRICATION OF GATE-ALL-AROUND VERTICALLY STACKED SILICON NANOWIRE FETS 1033
Fig. 7. Logarithmic plot for the same device conditions of Fig. 6. Both n- and
p-type device branches show subthreshold slopes SS ≤ 70 mV/dec. I
on
/I
off
ratios of ≈ 10
7
(≈ 10
6
) are obtained, respectively, for the n-type (p-type)
conduction branches.
scheme. Specifically, in Fig. 2, band bending at the S/D contacts
is shown for weakly p-doped silicon nanowires. Subthreshold
slopes of 64 mV/dec and 70 mV/dec were obtained, respectively,
for the p-type and n-type conduction branches in the same phys-
ical device. Moreover, I
on
/I
off
values range from 10
6
to 10
7
,
respectively, for the p-type and n-type conduction branches still
in the same device. Note that, in this device, we employed ma-
terials (NiSi S/D) and low p-doped channel, in order to obtain
a crossing between n- and p-type characteristics at V
pg
> 0V.
Specifically, we wanted to obtain a device, which behaves al-
ready as p-type for V
pg
=0V, while switching to n-type for a
low positive V
pg
(e.g., V
pg
=1Vto V
pg
=2V).
B. SB Height Extraction
Schottky contact barrier height extraction was performed on
the device of Fig. 6. Among different techniques used to mea-
sure the SB height (i.e., capacitance–voltage, current–voltage,
photoelectric method, etc.), we selected the activation energy
approach, both for its accuracy and for its independence from
the electrically active area. This second aspect makes it par-
ticularly well suited to study silicide–semiconductor interfaces.
Assuming negligible parasitics resistances, the thermionic emis-
sion theory can be applied to the barrier extraction
I = I
0
exp
qV
ηk
BT
− 1
I
0
= AA
2
0T
exp
−qΦ
B
k
B
T
where A is the contact area of the source to channel junction,
A
0
the Richardson constant, q the elementary electron charge,
φ
0
B
the effective SB height, T the temperature, V the applied
voltage across the Schottky junction, k
B
the Boltzmann con-
stant, and η the ideality factor.
In Fig. 8, some of the experimental results of I
DS
current
measurements at different temperatures are shown. The linear
decreasing slope of the Arrhenius plot in Fig. 9, fitted within
5% error in experimental data with a measured ideality factor
η =1.84, indicates thermionic emission regime. Near-midgap
Fig. 8. Selection of the performed measurements at different temperatures,
used for SB height extraction, at V
ds
= 100 mV and for (a) V
pg
= −4 Vand
(b) V
pg
=4V. Quasi-symmetric device operation can be observed.
Fig. 9. Arrhenius plot extracted from measurements, some of which are repre-
sented in Fig. 8. The linear decreasing slope of the plot, fitted within 5% error in
experimental data, indicates thermionic emission regime. qΦ
B
p
barrier height
of 0.45 eV is observed, confirming that the type of Silicide is compatible with
the expected NiSi, whose barrier height value on p-Si is ∼0.4 eV. In the inset,
energy-band diagram of metal on p-type semiconductor at thermal equilibrium,
showing the qΦ
B
p
barrier.
Schottky (qΦ
B
p
) barrier height of 0.45 eV is observed, confirm-
ing that the type of silicide is compatible with the expected
NiSi, whose barrier height value on p-Si is ∼ 0.4 eV. This
value is consistent both with the literature and simulation re-
sults. In the inset of Fig. 9, the energy-band diagram of metal–
p-type semiconductor junction at thermal equilibrium is repre-
sented, showing the qΦ
B
p
barrier. Compared to previous art (see
Table I), our device shows excellent I
on
/I
off
and subthreshold
slopes, combined with a high degree of symmetry between the
n and p conduction branches. Moreover, the device shows a nor-
mally p-type ON state, when V
pg
= V
cg
=0V. This is due to
the alignment of the S/D metal workfunction to the conduction
band of the SiNWs, as shown in the bottom case of Fig. 2, and
is achieved using weakly p-doped nanowires. As described in
the following sections, this feature enables the fabrication of
cascadable logic gates.
C. Device Simulation
After measuring the fabricated devices, we built a TCAD
model using the same device architecture. The model was fitted
