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Unequal Error Protection of Memories in LDPC Decoders

TLDR
The devised UEP method is divided in four adjustable levels, each one offering a different degree of protection, and shows an unmatched level of protection from errors at a small complexity and energy cost.
Abstract
Memories are one of the most critical components of many systems: due to exposure to energetic particles, fabrication defects and aging they are subject to various kinds of permanent and transient errors. In this scenario, Unequal error protection (UEP) techniques have been proposed in the past to encode stored information, allowing to detect and possibly recover from errors during load operations, while offering different levels of protection to partitions of codewords according to their importance. Low-density parity-check (LDPC) codes are used in many communication standards to encode the transmitted information: at reception, LDPC decoders heavily rely on memories to store and correct the received information. To ensure efficient and reliable decoding of information, the need to protect the memories used in LDPC decoders is of primary importance. In this paper we present a study on how to efficiently design UEP techniques for LDPC decoder memories. The devised UEP method is divided in four adjustable levels, each one offering a different degree of protection. The full UEP, along with simplified versions, has been implemented within an existing decoder and its area occupation and power consumption evaluated. Comparison with the literature on the subject shows an unmatched level of protection from errors at a small complexity and energy cost.

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Citations
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Journal ArticleDOI

ACOCO: Adaptive Coding for Approximate Computing on Faulty Memories

TL;DR: The Adaptive Coding for approximate Computing (ACOCO) framework is presented, which provides an analysis-guided design methodology to develop adaptive codes for different computations on the data read from faulty memories.
Journal ArticleDOI

SEFI Protection for Nanosat 16-Bit Chip Onboard Computer Memories

TL;DR: Two solutions are presented to protect a nano/pico satellite onboard computer memory prototype with 16-bit data words against SEFIs and SEUs and the approach to provide the error-correction capabilities is based on orthogonal latin square codes.
Proceedings ArticleDOI

Low-power LDPC decoder design exploiting memory error statistics

TL;DR: Simulation results of the proposed low-power LDPC decoder technique demonstrate that, by deliberately adjusting the scaled supply voltage to memory bits in different memory locations, the memory power consumption as well as the overall energy consumption of the LD PC decoder can be significantly reduced with negligible performance loss.
References
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Proceedings ArticleDOI

Optimized unequal error protection for voice over IP

TL;DR: Recognizing the unequal perceptual importance of voice packets, signal-adaptive unequal error protection methods in which certain packets are allocated more error-control resources than others are proposed.
Proceedings ArticleDOI

Unequal error protection for wireless transmission of MPEG audio

TL;DR: Simulation results show that the proposed scheme reduces the frame error rate by a factor of 2 and lowers the peak-subband-error-power-to-mask ratio of the audio data by as much as 11 dB.
Proceedings ArticleDOI

Unequal-error-protection codes in SRAMs for mobile multimedia applications

TL;DR: A novel metric, word mean squared error, is used, to measure the reliability of a SRAM word when different bits are not equally significant, and an optimization algorithm based on dynamic programming is constructed to construct the UEPECC that assigns different protection levels to bits according to their significance.
Proceedings ArticleDOI

Energy-Efficient LDPC Decoders Based on Error-Resiliency

TL;DR: This paper presents an energy-efficient LDPC decoder based on statistical error compensation (SEC), which can operate at a supply voltage up to 38% less than the nominal voltage and tolerate up to 30× more errors over an SNR range of 3dB to 8dB, while maintaining less than 3× degradation in BER.
Proceedings ArticleDOI

Multiple Upsets Tolerance in SRAM Memory

TL;DR: The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead.
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Q1. What have the authors contributed in "Unequal error protection of memories in ldpc decoders" ?

Memories are one of the most critical components of many systems: due to exposure to energetic particles, fabrication defects and aging they are subject to various kinds of permanent and transient errors. In this paper the authors present a study on how to efficiently design UEP techniques for LDPC decoder memories.