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Unequal Error Protection of Memories in LDPC Decoders

TLDR
The devised UEP method is divided in four adjustable levels, each one offering a different degree of protection, and shows an unmatched level of protection from errors at a small complexity and energy cost.
Abstract
Memories are one of the most critical components of many systems: due to exposure to energetic particles, fabrication defects and aging they are subject to various kinds of permanent and transient errors. In this scenario, Unequal error protection (UEP) techniques have been proposed in the past to encode stored information, allowing to detect and possibly recover from errors during load operations, while offering different levels of protection to partitions of codewords according to their importance. Low-density parity-check (LDPC) codes are used in many communication standards to encode the transmitted information: at reception, LDPC decoders heavily rely on memories to store and correct the received information. To ensure efficient and reliable decoding of information, the need to protect the memories used in LDPC decoders is of primary importance. In this paper we present a study on how to efficiently design UEP techniques for LDPC decoder memories. The devised UEP method is divided in four adjustable levels, each one offering a different degree of protection. The full UEP, along with simplified versions, has been implemented within an existing decoder and its area occupation and power consumption evaluated. Comparison with the literature on the subject shows an unmatched level of protection from errors at a small complexity and energy cost.

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Citations
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Journal ArticleDOI

ACOCO: Adaptive Coding for Approximate Computing on Faulty Memories

TL;DR: The Adaptive Coding for approximate Computing (ACOCO) framework is presented, which provides an analysis-guided design methodology to develop adaptive codes for different computations on the data read from faulty memories.
Journal ArticleDOI

SEFI Protection for Nanosat 16-Bit Chip Onboard Computer Memories

TL;DR: Two solutions are presented to protect a nano/pico satellite onboard computer memory prototype with 16-bit data words against SEFIs and SEUs and the approach to provide the error-correction capabilities is based on orthogonal latin square codes.
Proceedings ArticleDOI

Low-power LDPC decoder design exploiting memory error statistics

TL;DR: Simulation results of the proposed low-power LDPC decoder technique demonstrate that, by deliberately adjusting the scaled supply voltage to memory bits in different memory locations, the memory power consumption as well as the overall energy consumption of the LD PC decoder can be significantly reduced with negligible performance loss.
References
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Journal ArticleDOI

Delayed Stochastic Decoding of LDPC Codes

TL;DR: A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) decoders, suitable for fully-parallel implementation of long LDPC codes with applications in optical communications.
Journal ArticleDOI

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

TL;DR: An LDPC decoder chip fully compliant to IEEE 802.16e applications and with only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes to enable parallel message to be routed without congestion.
Proceedings ArticleDOI

FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding

TL;DR: An application-specific instruction-set processor (ASIP) which supports convolutional codes, binary/duo-binary turbo codes, and LDPC codes is presented, outperforming existing ASIP solutions for LDPC decoding by an order of magnitude.
Posted Content

Self-Corrected Min-Sum decoding of LDPC codes

TL;DR: A very simple but powerful self-correction method for the min-sum decoding of LPDC codes that modifies the variable node processing by erasing unreliable messages, and shows that this positively affects check node messages, which become symmetric Gaussian distributed, and is sufficient to ensure a quasi-optimal decoding performance.
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Q1. What have the authors contributed in "Unequal error protection of memories in ldpc decoders" ?

Memories are one of the most critical components of many systems: due to exposure to energetic particles, fabrication defects and aging they are subject to various kinds of permanent and transient errors. In this paper the authors present a study on how to efficiently design UEP techniques for LDPC decoder memories.